An integrated interface for an electronic device without a USB port includes at least one SIM card interface drive chip, a USB interface control chip, at least one SIM card interface control chip electronically connected to the at least one SIM card interface drive chip and the USB interface control chip, and a USB interface drive chip electronically connected to the USB interface control chip. A detection signal pin is defined on the USB interface control chip. When the detection signal pin is triggered, the USB interface control chip is turned on and the SIM card interface drive chip is turned off. When triggered, the USB interface drive chip drives the USB interface control chip to work, allowing access by an external whole-machine probe or test device.

The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

A test and measurement probe coupler that may include a substrate, a first signal tap conductor, a first signal contact, a first ground tap conductor, and a first ground contact. The first signal tap conductor may extends a first length along the substrate. The first signal contact may be electrically coupled to the first signal tap conductor, and the first ground tap conductor may extend a second length along the substrate. The first ground tap conductor may be substantially parallel to the first signal tap conductor. The first ground tap conductor may be disposed in a first lateral direction away from the first signal tap conductor, and the first ground contact electrically may be coupled to the first ground tap conductor.

A fixture for testing coaxial connectors for PIM includes: (a) an adapter connector comprising an inner contact; an outer body that circumferentially surrounds and that is spaced from the inner contact, the outer body including an inner ring and an outer ring with a gap therebetween; and a resilient member in electrical contact with the outer body; and (b) a foundation including a fixed sleeve and a biasing member, the biasing member exerting an axial force on the sleeve and the outer body, the biasing member permitting axial and radial adjustment of the outer body and inner contact relative to the sleeve. The gap between the inner and outer rings of the outer body is configured to receive an outer ring of an outer body of a coaxial connector to be tested. The inner ring of the test fixture is located to be radially outward of an inner ring of the outer body of the coaxial connector to be tested. The resilient member is positioned to apply radial pressure to the inner ring of the outer body of coaxial connector to be tested.

The present invention provides a test method, a tester, a load board and a test system. The test method includes: outputting, through a first input/output (I/O) port of a tester, a first test signal to a first channel of a load board, wherein the first test signal is used to generate a second test signal and a third test signal; receiving, through the first I/O port, a third feedback signal returned from the first channel, wherein the third feedback signal is generated based on a first feedback signal and a second feedback signal; and determining whether a first chip and a second chip are operating normally based on the third feedback signal. Solutions provided in the present invention are capable of increasing the number of chips that can be tested at a single time.

In described examples, a method of determining whether there is an open load fault in a test circuit includes closing a first switch to couple an input voltage to a first LC filter in which a first capacitor is coupled to a ground, the first LC filter coupled to a first terminal coupled to the test circuit; and closing a second switch to couple the input voltage to a second LC filter in which a second capacitor is coupled to the ground, the second LC filter coupled to a second terminal coupled to the test circuit. After the LC filters charge to the input voltage, the second switch is opened, and the second capacitor is discharged across a discharge resistor for a specified discharge time. The voltage across the discharge resistor falling below a reference voltage indicates that there is an open load fault in the test circuit.

A chip testing device for being transferred among a plurality of working stations includes a circuit board, a control set, and a plurality of connection terminals. The circuit board is provided with a plurality of electrical connection sockets disposed thereon each for carrying a chip. The control set includes a plurality of testing modules disposed on the circuit board. The connection terminals are disposed on the circuit board. When the connection terminals are connected to an external power supply device, the testing modules are connected to the electrical connection sockets, and each of the testing modules is able to test the chip on the electrical connection socket connected thereto.

A scalable test platform can include one or more of a plurality of different device interface boards and a plurality of primitives. The different device interface boards can be configured to provide a uniform interface to couple different types of DUTs and or DUTs with different form factors to the plurality of primitives. The plurality of primitives can be configured to distribute power to the DUTs, and to perform system level testing of the respective DUTs. The plurality of primitives can be configurable by a user to perform any number of system level tests on a number of different types of DUTs and or DUTs with different form factors.

A method of testing a semiconductor device having a DC line configured to carry either a DC signal or a DC voltage and a circuit electrically connected to the DC line includes: during a first part of a test sequence, enabling a switch device so as to electrically connect a capacitor to the DC line via the switch device and applying a test signal to the circuit while the capacitor is electrically connected to the DC line; and during a second part of the test sequence, disabling the switch device so as to electrically disconnect the capacitor from the DC line via the switch device, injecting an AC signal onto the DC line after the capacitor is electrically disconnected from the DC line, and measuring a response of the circuit to the AC signal.

A test board is provided including a first branch line including a first portion which receives an input signal and a second portion opposite to the first portion. A plurality of second branch lines branch from the first branch line. Each of the second branch lines include a third portion connected to the second portion of the first branch line and a fourth portion connected to the third portion. A first characteristic impedance of the first portion of the first branch line is different from a second characteristic impedance of the second portion of the first branch line. A third characteristic impedance of the third portions of each of the second branch lines is different from a fourth characteristic impedance of the fourth portions of each of the second branch lines. The second characteristic impedance is equal to a combined characteristic impedance of the third portions of each of the second branch lines.