A power supply for supplying a power to a heating mechanism used for heating a measurement target that emits a measurement signal includes an input device configured to output an input signal that reflects a control signal in a differentiable periodic waveform having a frequency of 1 kHz or less. The power supply includes a switching amplifier configured to amplify the input signal from the input device and output the amplified signal.

A method for estimating the aging of an electronic component, characterized in that it includes the following steps: —compiling a thermal specification of the electronic component in order to determine a reference lifetime, —determining a reference temperature quantity, —measuring the actual temperature of the electronic component in operation, —determining an actual temperature quantity, —determining an equivalent operating time at the actual temperature, —transposing this equivalent operating time to the reference temperature to obtain a transposed operating time, —summing the transposed operating times to obtain a consumed lifetime comparable to the reference lifetime.

A method for assessing the state of damage of a semiconductor module that is subject to operational loading, in particular a semiconductor module of a drive system converter, that includes at least one semiconductor component arranged on or in a support structure. It is possible not only to estimate a spent service life for the entire semiconductor module, but also to detect unexpected or undesirable loading states and thus a premature reduction of the remaining service life of the semiconductor module. Continuous load assessments are thus possible already during the operation of the semiconductor module and allow interventions to be made in good time.

The present invention proposes a chip reliability test assembly, which comprises a motherboard and a daughter board. The motherboard is used to support the chips during an aging acceleration process at high temperature. The daughter board is used to measure the electricity of chip after the aging acceleration process. Each chip holder is removable off the motherboard. The daughter board does not go through the aging acceleration process and can be reusable.

An electronic device includes: a detection circuit configured to determine one or more operating data, one or more device sensor data, or a combination thereof associated with operation of the electronic device; a trigger circuit operably coupled to the circuit, the trigger circuit configured to generate a stress input based on detecting one or more target criteria from the one or more operating data, the one or more device sensor data, or a combination thereof; and a degradation sensor operably coupled to the trigger circuit, the degradation sensor having a threshold voltage and being configured to record the target criteria that occurs during operation of the electronic device, wherein the degradation sensor is configured to record the target criteria based on degradation of the threshold voltage according to the stress input.

Various embodiments of the invention provide a system and a method for testing one or more devices under test (DUTs) and for checking one or more test setups. Each of the one or more test setups includes a test board having several sockets for receipt of a DUT. A custom hardware interface is used to electrically connect the test board, such as a burn-in board with a test system configuration having multiple modules that can be configured using a computer device and related software to provide customized testing of the DUTs. The system is scalable to accommodate any DUT having any number of channels and to provide customized testing. Results of the testing are sent to the computing device.

Embodiments provide a ring oscillator and test method. The ring oscillator includes a first logic gate, a second logic gate, and a switch circuit. The first logic gate is configured to receive a test signal. The second logic gate includes a first NAND gate and a first NOR gate connected in sequence. An output terminal of the second logic gate is connected to an input terminal of the first logic gate, and the second logic gate is configured to receive output of the first logic gate to form a loop. The switch circuit includes a first switch circuit and a second switch circuit. The first switch circuit may be configured to control on/off of a power supply terminal of the first NAND gate and a ground terminal of the first NOR gate. The second switch circuit is configured to control on/off of a ground terminal of the first NAND gate.

A system includes a signal generator, configured to pass a generated signal, which has two different generated frequencies, through a circuit including an intrabody electrode. The system further includes a processor, configured to identify, while the generated signal is passed through the circuit, a derived frequency, which is derived from the generated frequencies, on the circuit, and to generate, in response to identifying the derived frequency, an output indicating a flaw in the electrode. Other embodiments are also described.

A high-pressure burn-in test apparatus comprises a burn-in furnace including a high-pressure burn-in furnace cavity equipped with a driving motor, at least one intake manifold, at least one extension manifold equipped with a nozzle, a communicating tube connected to the intake manifold, and a fan. A processing chamber having a test board is formed inside the high-pressure burn-in furnace cavity. The periphery of at least one of the intake manifold is connected to the at least one extension manifold. At least one component to be tested is placed on the test board. High-pressure gas is ejected through the nozzle to disturb the gas around the component to be tested. The fan is installed in the processing chamber. The driving motor drives the fan to rotate, so that the gas in the processing chamber generates convection, to improve the uniformity of gas temperature distribution.

Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.