Systems and methods for semiconductor design evaluation. IC layout information of a circuit design is received, and the circuit design is decomposed into smaller circuit pieces. Each circuit piece has IC layout information and a netlist. For each circuit piece, a set of strike models is selected based on the layout information and the net-list of the circuit piece and received radiation environment information. Each strike model has circuit components with voltage values corresponding to a respective particle strike. For each selected strike model of a circuit piece: a radiation susceptibility metric is determined by comparing functional results of simulation of the of the strike model with functional results of simulation of the circuit piece. For each circuit piece, a radiation susceptibility metric is determined based on the radiation susceptibility metrics generated for each selected strike model of the circuit piece.

A thermal management system for a test-and-measurement probe that includes a thermally insulated shroud and a fluid inlet conduit. The shroud is configured to enclose a first portion of a probe head of the probe within an interior cavity of the shroud, while permitting a second portion of the probe head to extend out of the shroud. The shroud further includes a fluid outlet passageway configured to permit a heat-transfer fluid to pass from a probe-head end of the interior cavity, through the interior cavity of the shroud, and out of the shroud through an access portion of the shroud. The fluid inlet conduit enters the shroud through the access portion of the shroud, extends through the interior cavity of the shroud, and is configured to introduce the heat-transfer fluid to the probe-head end of the interior cavity.

A test board is provided including a first branch line including a first portion which receives an input signal and a second portion opposite to the first portion. A plurality of second branch lines branch from the first branch line. Each of the second branch lines include a third portion connected to the second portion of the first branch line and a fourth portion connected to the third portion. A first characteristic impedance of the first portion of the first branch line is different from a second characteristic impedance of the second portion of the first branch line. A third characteristic impedance of the third portions of each of the second branch lines is different from a fourth characteristic impedance of the fourth portions of each of the second branch lines. The second characteristic impedance is equal to a combined characteristic impedance of the third portions of each of the second branch lines.

Systems and methods for semiconductor design evaluation. IC layout information of a circuit design is received, and the circuit design is decomposed into smaller circuit pieces. Each circuit piece has IC layout information and a netlist. For each circuit piece, a set of strike models is selected based on the layout information and the net-list of the circuit piece and received radiation environment information. Each strike model has circuit components with voltage values corresponding to a respective particle strike. For each selected strike model of a circuit piece: a radiation susceptibility metric is determined by comparing functional results of simulation of the of the strike model with functional results of simulation of the circuit piece. For each circuit piece, a radiation susceptibility metric is determined based on the radiation susceptibility metrics generated for each selected strike model of the circuit piece.

An apparatus and a method provide a high temperature test and a low temperature test. The apparatus mainly includes a depressing head and a test base, wherein the depressing head includes a cooling module, a heating module, and a heat dissipation module therein, the heat dissipation module includes a finned heat sink and a heat conduction member, and the heat conduction member is thermally coupled to the heating module and the finned heat sink. When the low temperature test is performed, an electronic component is cooled by filling liquid nitrogen into the cooling module of the depressing head. When the high temperature test is performed, the electronic component is heated by the heating module. If the temperature of the electronic device is higher than a predetermined high temperature, the electronic device is cooled by the heat dissipation module.

A chip testing method for being implemented by a chip testing system includes: a chip mounting step implemented by using a chip mounting apparatus to respectively dispose a plurality of chips onto electrical connection sockets of a chip testing device; a moving-in step implemented by transferring the chip testing device carrying the chips into one of accommodating chambers of an environment control apparatus; a temperature adjusting step implemented by controlling a temperature adjusting device of the one of the accommodating chambers so that the chips are in an environment having a predetermined temperature; and a testing step implemented by providing electricity to the chip testing device, so that each testing module of the chip testing device performs a predetermined testing process on the chips on the corresponding electrical connection sockets connected thereto.

A device for testing performance of main boards of electronic devices includes a housing, two bases, a control device, a humidifier, a heating device, and a refrigerating device. A cavity in the housing comprises separated first and second portions. The heating device is interconnected with the first portion to create a predefined high temperature environment and the refrigerating device is interconnected with the second portion to create a predefined low temperature environment. The humidifier is interconnected with the first portion and the second portion, and configured to create predefined degrees of humidity respectively in the first portion and the second portion. The bases are inside the first portion and the second portion, and electrically connected to the control device.

The present disclosure relates to a device for simulating a battery of a device-under-test (DUT), comprising a battery simulation unit adapted to fit into a battery reception unit of the DUT; and a controller configured to control the battery simulation unit to simulate electrical characteristics of a battery; wherein the battery simulation unit is configured to supply electrical power to the DUT or drain electrical power from the DUT based to the simulated electrical characteristics. The device further comprises a temperature sensor configured to measure a temperature at or in the battery simulation unit; and a heater unit configured to heat the battery simulation unit.

A system for reducing low cycle fatigue of a soldered connection includes a controller and a heating element operatively connected to the controller. The system also includes a printed wire board soldered in connection with an electronic component. The controller is configured to retrieve a signal indicative of a temperature of the electronic component, and compare the temperature to a stored predetermined range of operating temperatures. Responsive to determining that the temperature of the electronic component is less than a lower threshold temperature of the predetermined range of operating temperatures, the controller transmits a signal to the heating element that causes the heating element to heat the electronic component. The controller then saves, to an operatively connected computer readable memory, a magnitude of temperature difference and a number of times that magnitude is reached. The controller uses the stored information to track the life of the electronic component.

In a power supply system, a high-side (HS) insulated-gate bipolar transistor (IGBT) has a first collector, a first gate, and a first emitter. A low-side (LS) IGBT has a second collector coupled to the first emitter, a second gate, and a second emitter. A gate drive circuit is coupled to the first gate of the HS IGBT and the second gate of the LS IGBT. A control circuit is coupled to the gate drive circuit. The control circuit is configured to control the gate drive circuit for biasing the HS IGBT to a HS saturation, and determine a HS degradation of the HS IGBT based on a HS digitized gate voltage of the HS IGBT in the HS saturation.