A semiconductor device includes a signal processing circuit configured to generate an output signal, an output pad, an output line connecting the signal processing circuit to the output pad, the output signal from the signal processing circuit being output from the output pad through the output line, a shorting pad formed in the output line, a switch connected between the shorting pad and the output pad, and configured to connect the signal processing circuit to the output pad when the switch is on, and disconnect the signal processing circuit from the output pad when the switch is off, and a wiring line connecting the shorting pad to the output pad.

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, and may include NCEM pads that comprise a mesh of GATECNT and AACNT stripes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

A semiconductor integrated circuit device (1000) includes: a first semiconductor chip CHP1 having a first circuit; and a second semiconductor chip (CHP2) having a second circuit and differing from the first semiconductor chip (CHP1). The semiconductor integrated circuit device (1000) further includes a control circuit (BTCNT) for controlling an operation of the first circuit and an operation of the second circuit in accordance with a control signal in a burn-in test, and the control circuit (BTCNT) controls the first circuit and the second circuit such that an amount of stress applied to the first semiconductor chip (CHP1) due to an operation of the first circuit and an amount of stress applied to the second semiconductor chip (CHP2) due to an operation of the second circuit differ from each other in the burn-in test.

A multi-channel device with a single diagnosis status pin may be configured to detect if one or more channels has a fault. The multi-channel device, which may operate within a system, can communicate which channel, of a plurality of channels, has the fault using only a single diagnosis status pin and no additional diagnosis control pins. The multi-channel device may output a fault signal on the diagnosis status pin and in response to an interrogation input signal on the same channel as a fault channel indicate to the system which channel is the fault channel.

A semiconductor chip includes a semiconductor device connected between a first node to which a power supply voltage is applied and a second node to which a ground voltage is applied, a first ring oscillator connected to the first node through a first supply switch and the second node through a first ground switch and a second ring oscillator connected to the first node through a second supply switch and the second node through a second ground switch, wherein the first supply and ground switches are configured to operate in response to a first control signal, thereby operating the first ring oscillator, and the second supply and ground switches are configured to operate in response to a second control signal, thereby operating the second ring oscillator.

A test structure and method to detect open circuits due to electromigration or burn-out in test wires and inter-level vias. Electromigration occurs when current flows through circuit wires leading to a circuit interruption within the wire. The test structure is a passive test wire arranged in one of several configurations within the circuit of a computer chip. The dimensions and resistances of test wires can vary according to the test structure configuration. Each test wire is measured for an electrical discontinuity after the computer chip is powered-on. If a wiring interruption is detected, it is concluded that the chip had been powered-on before.

Disclosed is an integrated circuit (IC) chip having an on-chip usable life depletion meter. This meter incorporates programmable bits, which represent units of usable life. These programmable bits are sequentially ordered from an initial programmable bit to a last programmable bit and are automatically programmed in order, as the expected usable life of the IC chip is depleted. These programmable bits are readable to determine the remaining usable life of the IC chip. Also disclosed is a method that uses the on-chip usable life depletion meter. In the method, the remaining usable life of an IC chip, once known, is used either as the basis for allowing re-use of the IC chip (e.g., for a non-critical application and when the remaining usable life is sufficient) or as the basis for preventing re-use of the IC chip (e.g., for a critical application or when the remaining usable life is insufficient).

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.

A semiconductor device includes: a plurality of semiconductor chips; and a connecting portion that connects a plurality of terminals formed on the plurality of semiconductor chips, wherein the plurality of terminals of the plurality of semiconductor chips belong to one of first group or second group, an interval between one of first terminals belonging to the first group and one of second terminals belonging to the second group is a predetermined interval, the one of the second terminals being adjacent to the one of the first terminal, the first terminals are arranged at an interval larger than the predetermined interval, and each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals, per each of the groups.

An IC is provided. The IC includes a power grid including M.sub.x layer interconnects extending in a first direction on an M.sub.x layer and M.sub.x+1 layer interconnects extending in a second direction orthogonal to the first direction on an M.sub.x+1 layer, where x>5. In addition, the IC includes a plurality of power switches. Further, the IC includes at least one sensing element located between the M.sub.x layer and the M.sub.x+1 layer and configured to measure a voltage drop to devices powered by the plurality of power switches. The one or more of the plurality of power switches may be located below the power grid. The power switches of the plurality of power switches may be adjacent in the first direction and in the second direction to each sensing element of the at least one sensing element.