A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.

This disclosure is directed to circuits and techniques for detecting or responding to temperature of a power switch. A driver circuit for the power switch may be configured to deliver a modulation signal to a control node of the power switch to control on/off switching of the power switch, wherein the driver circuit is further configured to modulate an output impedance of the driver circuit at the control node, perform one or more voltage measurements while modulating the output impedance of the driver circuit, and control the power switch based at least in part on the one or more voltage measurements.

The disclosure describes techniques for detecting failures or performance degradation of a device including an integrated circuit (IC) components in the field by including additional contacts, i.e. terminals, along with functional contacts of the circuit used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be internal external to the package surface and may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, capacity, temperature and impedance. These electrical characteristics may be representative of one or more failure modes and may be treated as indicator for device state-of-health (SOH).

This disclosure is directed to circuits and techniques for detecting or responding to temperature of a power switch. A driver circuit for the power switch may be configured to deliver a modulation signal to a control node of the power switch to control on/off switching of the power switch, wherein the driver circuit is further configured to modulate an output impedance of the driver circuit at the control node, perform one or more voltage measurements while modulating the output impedance of the driver circuit, and control the power switch based at least in part on the one or more voltage measurements.

The disclosure describes to techniques for detecting field failures or performance degradation of circuits, including integrated circuits (IC), by including additional contacts, i.e. terminals, along with the functional contacts that used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, temperature and impedance. These electrical characteristics may be representative of a certain failure mode and may be an indicator for circuit state-of-health (SOH), while the circuit is performing in the field.

The disclosure describes techniques for detecting failures or performance degradation of a device including an integrated circuit (IC) components in the field by including additional contacts, i.e. terminals, along with functional contacts of the circuit used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be internal external to the package surface and may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, capacity, temperature and impedance. These electrical characteristics may be representative of one or more failure modes and may be treated as indicator for device state-of-health (SOH).

A test circuit includes one or more sensors adapted to be formed on a wafer, each sensor detecting one or more reliability measurement data in a stressed condition; a stress generator controlling the one or more sensors to place the one or more sensors under stress during wafer manufacturing; memory coupled to the one or more sensors to store reliability characteristics under the stressed condition; and an interface coupled to the memory to communicate the wafer characterization data to a tester.

A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.

The subject disclosure relates to a system and method for testing units-under-test (UUT) with a thermal shock. The thermal shock testing system can include a chamber having an inlet and an outlet, the chamber being configured to provide a thermal shock to a unit-under-test (UUT), a pump configured to fluidly connect to the inlet of the chamber and direct a temperature controlled liquid through a channel embedded in the chamber, and a boiler and a chiller fluidly connected to the pump, the temperature of the liquid being controlled by at least one valve configured to alternatively direct hot or cold fluid to the inlet of the chamber.

Systems, methods, apparatuses, and computer program products for audio output device testing. For example, some embodiments described herein may provide for audio output device testing in an objective and consistent manner Specifically, some embodiments may provide a system that can be used to determine an array of tests for an audio output device, cause the audio output device to be tested according to the array of tests, compare a performance of the audio output device to a baseline performance, and intelligently and objectively determine a score for the audio output device. In addition, the system may trigger, or perform, certain actions with respect to the audio output device based on the score.