G01R31/2872

Method of testing semiconductor device
11029356 · 2021-06-08 · ·

A first relational expression for a temperature of a semiconductor device and forward voltage of a temperature measurement diode is obtained in advance. A second relational expression is obtained in advance for ON voltage of the semiconductor device and an amount of temperature change from a first time point before ON of the semiconductor device until a second time point after OFF of the semiconductor device. An amount of forward voltage change of the temperature measurement diode from the first time point until the second time point is obtained. Next, the amount of temperature change from the first time point until the time second point is calculated using the first relational expression and the amount of forward voltage change. An ON voltage of the MOS gate semiconductor device after correction for the calculated amount of temperature change is obtained using the second relational expression.

IC with insulating trench and related methods

A method of making an integrated circuit (IC) includes forming circuitry over a top surface of a semiconductor substrate having the top surface and an opposite bottom surface. An antenna is formed in an interconnect layer formed above the semiconductor substrate, where the antenna is coupled to circuitry. A seal ring is formed around a periphery of the interconnect layer. The seal ring is disposed around the antenna and the circuitry. A trench with a solid-state insulating material is formed. The trench extends vertically into the semiconductor substrate and extends laterally across the IC.

Soft error inspection method, soft error inspection apparatus, and soft error inspection system
11054460 · 2021-07-06 · ·

A soft error inspection method for a semiconductor device includes: irradiating and scanning the semiconductor device with a laser beam or an electron beam; and measuring and storing a time of bit inversion for each of areas irradiated with the laser beam or the electron beam of the semiconductor device.

Apparatus for testing electronic devices

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

APPARATUS FOR TESTING ELECTRONIC DEVICES

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

ELECTRICAL OVERSTRESS DETECTION DEVICE

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

METHOD FOR DETECTING AND CONTROLLING BATTERY STATUS BY USING SENSOR, AND ELECTRONIC DEVICE USING SAME

Various embodiments of the present invention relate to a method for detecting and controlling a battery status by using a sensor, and an electronic device using the same, the electronic device comprising: a housing; an accommodation part arranged inside the housing and including at least one gas sensor; a battery arranged inside the housing; a memory for storing information, acquired by the at least one gas sensor, on gas leaked from the battery and operation control information of the electronic device; and a processor electrically connected to the memory, wherein the processor is configured to acquire a detection signal of gas leaked from the battery by using the at least one gas sensor, and control the operation of at least a part of the electronic device and/or charging characteristics of the battery when the acquired gas detection signal exceeds a predetermined threshold value, so as to detect, in real time, a gas leakage of the battery occurring because of the exposure of the electronic device to high temperature or heat generation and control the battery status, thereby preventing safety accidents caused by the battery. Other various embodiments in addition to the disclosed various embodiments in the present invention are possible.

Apparatus for testing electronic devices

An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Substrate inspection device
10845409 · 2020-11-24 · ·

A substrate inspection device includes: a holding member configured to hold a probe card; a plate-shaped chuck facing the probe card and configured to place a substrate thereon; and an inspection chamber in which the holding member and the chuck are disposed. The substrate is brought into contact with the probe card by moving the chuck closer to the holding member. A sealed space is formed between the holding member and the chuck. A contact state between the probe card and the substrate are maintained by decompressing the sealed space. A gas introduction path is provided separately from the inspection chamber and configured to introduce a gas in a partitioned space into the sealed space, and the partitioned space is filled with a dry gas.

Burn-in preform and method of making the same

Some implementations are directed to a burn-in solder preform including: a barrier layer to prevent thermally conductive material from adhering to a semiconductor component during burn-in testing; and a thermally conductive cladding layer attached to a portion of the barrier layer such that at least one dimension of the barrier layer extends past the thermally conductive cladding layer, where the thermally conductive cladding layer is attached over the barrier layer through continuous attachment or spot attachment. In some implementations, a method includes: placing the aforementioned burn-in solder preform between a test fixture and a semiconductor component; attaching a portion of the barrier layer of the burn-in solder preform to a head of the text fixture; and after attaching a portion of the barrier layer of the burn-in solder preform to the head of the test fixture, performing burn-in testing of the semiconductor component.