A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

Provided is a semiconductor inspection device capable of high-speed response analysis as defect analysis of a fine-structured device constituting an LSI. Therefore, the semiconductor inspection device includes a vacuum chamber 3, a sample table 4 which is disposed in the vacuum chamber and on which a sample 6 is placed, an electron optical system 1 disposed such that an electron beam is emitted from above the sample, a plurality of probe units 24 connected to external devices 11 and 12 disposed outside the vacuum chamber via a coaxial cable 10, and an electrode 5 provided on or in the vicinity of the sample table. The probe unit 24 includes a measurement probe 8 configured to come into contact with the sample, a GND terminal 9 configured to come into contact with the electrode 5, and a probe holder 7 configured to hold the measurement probe and the GND terminal, connect a signal line of the coaxial cable to the measurement probe, and connect a GND line of the coaxial cable to the GND terminal. When the measurement probe of the probe unit comes into contact with the sample, the GND terminal comes into contact with the electrode.

A test apparatus includes a motherboard including a first surface. The test apparatus further includes a handler including a second surface facing the first surface of the motherboard. The test apparatus additionally includes an adapter board disposed between the first surface of the motherboard and the second surface of the handler. The test apparatus further includes a first sensor mounted on the adapter board and senses data about temperature of the adapter board. The test apparatus additionally includes a wireless transceiver mounted on the adapter board and transmits, in real time, the sensed data.

The present application provides a parameter setting method and apparatus, a system, and a storage medium. The parameter setting method includes: obtaining first setting values of multiple memory parameters and storage locations of the multiple memory parameters in a non-volatile memory; generating a first parameter setting instruction according to the first setting value and the storage location of each memory parameter; and sending the first parameter setting instruction to a test device, so that the test device sets the memory parameter stored at the storage location in the non-volatile memory as the first setting value.

A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

A semiconductor device test apparatus for improving a loss rate of a test signal in testing a device under test is provided. The semiconductor device test apparatus includes a probe interface board, a pogo block disposed on the probe interface board and electrically connected to a device under test, an equipment board disposed under the probe interface board, an alternating current (AC) controller, transferring and receiving an AC signal for performing an AC test on at least one of the device under test and the pogo block, being mounted on the equipment board, and a physical layer equalizing (PLE) board disposed between the probe interface board and the equipment board, a first equalizing circuit, decreasing loss of the AC signal, being mounted on the PLE board.

An automated test equipment for testing one or more DUTs comprises a test head and a DUT interface. The DUT interface comprises a plurality of blocks of spring-loaded pins, for example groups or fields of spring-loaded pins. For example, the DUT interface is configured for establishing an electronic signal path between the test head and a DUT board or load board, which holds the DUT or which provides a connection to the DUT. The automated test equipment is configured to allow for a variation of a distance between at least two blocks of spring-loaded pins.

In some embodiments, a method may include an area-aware optimization for the test patterns. The method may include dividing the chip area into a grid. The grid may be based on the smallest particle size. The method may include preparing test patterns and identifying a subset of test patterns that touch all of the grid locations. The subset may include a minimum number of test patterns from the prepared test patterns which when implemented exercise the all of the grid locations. The method allows to more quickly determine chips that fail due to extrinsic defects. Once a test fails during the testing process for a chip, testing on the chip is stopped and testing begins on the next chip. Rapidly identifying chips that fail due to extrinsic failures can decrease the overall test time and identify those that will fail quickly as the chip process matures and is dominated by extrinsic failures.