A reduced pin count (RPC) device includes an electrical circuitry in a package with uniformly distributed leads, a subset of the leads being electrically disconnected form the circuitry. A contactor pin block with sockets corresponding to the uniformly distributed leads has the sockets corresponding to the leads with electrical connections filled with test pins suitable for contacting respective leads, and the sockets corresponding to the electrically disconnected leads voided of test pins. Dummy plugs are inserted into the voided sockets to block the sockets and prevent accidental insertions of test pins.

The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

Herein disclosed are a method and a test probe for testing an electrical component. The electrical component comprises at least a first electrode and a second electrode. The method comprises the following steps: covering the first electrode with a first conducting flexible layer; driving a first electrode contact to electrically connect a first end of the first electrode contact with the first electrode via the first conducting flexible layer; covering the second electrode with a second conducting flexible layer; and driving a second electrode contact to electrically connect a second end of the second electrode contact with the second electrode via the second conducting flexible layer. The first conducting flexible layer is an anisotropic conductive film.

A testing device for electronic dies includes a first support part and a second support part configured to be removably assembled with each other. The first and second support parts together define at least one housing where at least one electronic die can be arranged to be tested. The electronic die has a first surface with contacting elements. The at least one housing includes a first portion. This at least one housing is arranged to enable the at least one electronic die to occupy a first position in the housing where the first surface is spaced apart from the first portion, and is further arrange to enable the at least one electronic die to occupy a second position in the housing where the first surface bears against the first portion.

A verification probe system is configured to verify an automated test platform and includes: an integrated circuit test probe assembly; and a moveable platform configured to position the integrated circuit test probe assembly proximate one of more conductive pins included within a test socket assembly of the automated test platform.

A storage unit is used for storing a plurality of interface units. A disposition system then automatically manages interface units. A carrier is provided for accommodating an interface unit. The interface unit is configured for testing semiconductor elements in corresponding test devices. The storage unit is designed for storing a plurality of interface units, the storage unit having a plurality of compartments, each for accommodating one carrier, and each such carrier being designed to accommodate one interface unit. The storage unit comprises at least one alignment element for positionally accurate coupling of a handling device.

A test system is provided. The system includes a first test apparatus and a second test apparatus. A device power supply of the first test apparatus (ATE) is electrically connected with a device under test (DUT) through a driving branch (F) and a detecting branch (S), the driving branch (F) being configured to provide an original driving current to the DUT b the device power supply during testing, and the detecting branch (S) being configured to detect an effective driving current reaching the DUT. The second test apparatus includes a first voltage drop branch, the first voltage drop branch is connected to the detecting branch (S), and a voltage drop detected by the driving branch (F) is used to determine an effectiveness of an electrical connection formed between the driving branch and the device under test, and an electrical connection formed between the detecting branch (S) and the DUT.

Disclosed herein are apparatuses and methods for mitigating sticking of units-under-test (UUTs). For example, in some embodiments, a probe card may include a probe landing pad, a guide plate having a hole therein, and a pushing mechanism. The pushing mechanism may include a pusher needle and a pusher needle support, the pusher needle support may be between the probe landing pad and the guide plate, and the pusher needle support may be controllable to cause the pusher needle to extend and retract through the hole in the guide plate.

An inspection apparatus includes a load port area in which a carrier accommodation chamber for accommodating a carrier that receives an inspection object is disposed; an inspection area in which a plurality of probe cards are respectively disposed under a plurality of inspection devices, and in which the probe card is pressed against an electronic device of the inspection object on a chuck top to inspect the electronic device; a transfer area in which a transfer mechanism transfers the inspection object onto the chuck top; and a plurality of probe card accommodation devices disposed in at least one of the load port area or the inspection area, each probe card accommodation device being capable of accommodating the probe card, and a number of the probe card accommodation devices being equal to or greater than a number of the probe cards.

Examples described herein provide a wearout card and a method for using the wearout card. The wearout card generally includes a first set of connectors configured to connect the testing apparatus to a testing controller, and a second set of connectors configured to connect the testing apparatus to a device under test (DUT). The wearout card can also include a memory configured to store identifying information of the testing apparatus and a use counter indicating a number of times different DUTs have been connected to the second set of connectors.