A contact probe includes a first plunger, a contact terminal, and a conductive member. The first plunger is contactable with one of an electrode of a semiconductor device and a pad of a test jig. The contact terminal is contactable with the other of the electrode of the semiconductor device and the pad of the test jig. The conductive member covers a part of the first plunger. The conductive member and the first plunger are provided to bring an end portion of the first plunger and the contact terminal into a conduction state when the end portion of the first plunger is pressed by a force smaller than a predetermined force, and bring the end portion of the first plunger and the contact terminal into a nonconduction state when the end portion of the first plunger is pressed by a force equal to or larger than the predetermined force.

A non-transitory computer-readable storage medium storing a n EMI calculation program that causes at least one computer to execute a process, the process includes inputting circuit information of a first circuit to a machine learning model; acquiring an EMI value at a certain frequency of the first circuit; selecting, based on an impedance characteristic of the first circuit and the EMI value at the certain frequency, first EMI information from a plurality of pieces of EMI information in each of which an impedance characteristic of each of a plurality of circuits is associated with EMI values at a plurality of frequencies of each of the plurality of circuits; and acquiring an EMI value at another frequency different from the certain frequency of the first circuit based on the EMI value at the certain frequency and the first EMI information.

A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.

A relay pogo contact first charged device model test head apparatus for relay-based contact first field induced charged device model testing has a ground plane of conductive material, a coaxial connector whose outer conductor electrically connects to the ground plane, a current-sensing element with one terminal electrically connects to the ground plane and the other terminal electrically connects to the center conductor of the coaxial connector, a switch where the first terminal electrically connects to a center conductor of the coaxial connector, and a probe with one end electrically connected to a second terminal of the switch and the other end exposed to contact external objects.

A chip testing apparatus and system suitable for performing testing on multiple chips in a chip cluster are provided. The chip testing apparatus includes a signal interface and a test design circuit. The signal interface transmits an input signal and multiple driving signals in parallel from a test equipment to each of the chips. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs a test data to the test equipment according to the output signals.

The invention relates to a contacting module (1) by means of which the individual electrical and optical inputs and outputs (A.sub.oC) of optoelectronic chips (2) are connected to the device-specific electrical and optical inputs and outputs of a test apparatus. It is characterized by a comparatively high adjustment insensitivity of the optical contacts between the chips (2) and the contacting module (1), which is achieved, for example, by technical measures which result in the optical inputs (E.sub.oK) of the chip (2) or on the contacting module (1) being irradiated in every possible adjustment position by the optical signal (S.sub.o) to be coupled in.

A heater substrate has an insulating substrate having a first surface and a second surface on the opposite side relative to the first surface and at least one heating element of spiral shape including plural heater wire pieces and positioned in or on the insulating substrate. The heating element of spiral shape has at least one adjustment section including a turn of all or some of the plural heater wire pieces. The plural heater wire pieces include a first heater wire piece and a second heater wire piece adjacent to the inner side of the first heater wire piece. In the adjustment section, the length of the first heater wire piece is smaller than the length of the second heater wire piece.

A circuit board for semiconductor test includes first and second sub-circuit boards, and an insulating dielectric layer therebetween. Each sub-circuit board includes a substrate and circuits including upper and lower contacts. The insulating dielectric layer includes through holes, and connecting conductors disposed therein and electrically connected with the upper and lower contacts of two sub-circuit boards. The circuit board is defined with central and peripheral regions. The lower contacts of the first sub-circuit board in the central region are electrically connected with a probe head. The upper contacts of the second sub-circuit board in the peripheral region are electrically connected with a tester, larger in pitch than the lower contacts of the first sub-circuit board in the central region, and larger in amount than the lower contacts of the first sub-circuit board in the peripheral region. The circuit board has great power test uniformity.

A burn-in board includes: a board; a socket mounted on the board; a connector attached to the board; a wiring system that is disposed in the board and that connects the socket and the connector; and a compensation circuit that connects to the wiring system and that compensates a frequency characteristic of a signal transmitted through the wiring system.

The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.