The present application discloses a semiconductor device with an interface structure and a method for fabricating the interface structure. The interface structure includes an interface board configured to be fixed onto and electrically coupled to a chuck of a testing equipment, and a first object positioned on a first surface of the interface board and electrically coupled to the interface board. The first object is configured to be analyzed by the testing equipment.

A semiconductor device for testing a device under test includes a circuit board, a plurality of probes disposed below the circuit board and facing the device under test, an integrated substrate disposed between the circuit board and the plurality of probes, and signal-transmitting module disposed on the circuit board and next to the integrated substrate. The plurality of probes is electrically coupled to the circuit board through the integrated substrate, and the signal-transmitting module transmits a test signal to the plurality of probes through the integrated substrate and the circuit board to perform a test to the device under test. Another semiconductor device including the integrated substrate and a manufacturing method thereof are provided.

A wafer includes a plurality of testing dies, a plurality of non-testing dies, and a dicing region. Each testing die includes: a first active area including one or more first active devices, and one or more first device pads electrically coupled to the one or more first active devices. Each non-testing die includes: a second active area including one or more second active devices, and one or more second device pads electrically coupled to the one or more second active devices. The dicing region includes one or more testing pads electrically coupled to the one or more first device pads. The one or more testing pads are arranged to receive one or more external probes for determining one or more characteristics of the one or more first active devices of the plurality of testing dies. The plurality of non-testing dies are electrically isolated from the dicing region.

An apparatus for probing a device-under-test (DUT) includes a fixture disposed over the DUT, a circuitry film disposed along a contour of the fixture, a first signal connector, and a plurality of probing tips disposed on the circuitry film and extending toward the device-under-test. The circuitry film includes a first portion attached to a top sidewall of the fixture, and the first signal connector is disposed on and electrically connected to the first portion of the circuitry film. The first signal connector is electrically coupled to the probing tips through the circuitry film. A method for probing a DUT is also provided.

An apparatus for testing a package-on-package type semiconductor package includes an upper test socket on which an upper package is mounted, the upper test socket being mounted on a pusher and connected to the lower package; a lower test socket mounted on a tester and connected to the lower package; and an adsorption pad coupled to the pusher and configured to adsorb and pressurize the lower package using a vacuum pressure, wherein the adsorption pad comprises a body part having a vacuum pressure passage formed therein; and an adsorption part having an adsorption hole corresponding to the vacuum pressure passage, and the body part is attached on a central portion of an upper surface of the adsorption part and an outer oil overflow-preventing part configured to trap silicon oil eluted from the body part is formed at an outer periphery the adsorption part.

Disclosed is a probe card for testing a wafer. The probe card includes a substrate and a block including an insulation portion and a conducting portion disposed on the insulation portion. Here, the insulation portion includes a via and a probe pin which comes into contact with an object to be tested. The conducting portion includes a contact point electrically connected to the substrate and a conducting pattern passing through the via and electrically connecting the contact point to the probe pin. A pitch between a plurality of such probe pins is smaller than a pitch between a plurality of such contact points. The block includes a plurality of unit blocks. The plurality of unit blocks each include the insulation portion and the conducting portion, and at least parts of the insulation portions of the unit blocks are arranged while being spaced apart from each other.

The present disclosure relates to a test apparatus for a package-on-package type semiconductor package including a lower test socket mounted on a tester, and connected to a lower package to electrically connect the lower package to the tester; a pusher configured to be able to be moved vertically by receiving a driving force from a driving unit; an upper test socket mounted on the pusher, and having an electro-conductive part installed below the upper package to be electrically connected to the upper package; a vacuum picker mounted on the upper test socket to be able to vacuum-adsorb the lower package; and an inelastic insulating sheet installed between the upper test socket and the upper package, having a through hole formed at a position thereof corresponding to the terminal of the upper package and the electro-conductive part.

A testing apparatus for Data Storage Devices (DSDs) includes a chassis and at least one interface module configured to be removably inserted into the chassis and house a plurality of interface boards. Each interface board includes a DSD connector for connecting a DSD to the interface board and a backplane connector for connecting to a backplane for communicating with a respective computing unit. In one aspect, the at least one interface module includes a housing and a plurality of openings in a side of the housing with each opening configured to receive a respective interface board. A plurality of guide member pairs is positioned to guide respective interface boards when inserted into respective openings such that the backplane connector is located at a respective predetermined location for connecting to the backplane. In another aspect, the interface boards are removable from the interface module.

A chip testing apparatus and system suitable for performing testing on multiple chips in a chip cluster are provided. The chip testing apparatus includes a signal interface and a test design circuit. The signal interface transmits an input signal and multiple driving signals in parallel from a test equipment to each of the chips. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs a test data to the test equipment according to the output signals.

A wafer includes a semiconductor substrate, multiple photonics devices and a test coupler. The multiple photonics devices are fabricated on the substrate and have multiple respective ports. The test coupler is disposed on the wafer and is configured to couple an optical test signal between a tester and the multiple ports of the multiple photonics devices during testing of the photonics devices.