An over-the-air (OTA) measurement system is described. The OTA measurement system includes a plurality of measurement antennas, a DUT positioner, and a controller (e.g., control circuit). The DUT positioner is configured to position a device under test at a test location. At least two measurement antennas of the plurality of measurement antennas are arranged at different distances from the test location. The at least two measurement antennas are arranged at different elevation angles and/or at different azimuth angles with respect to the test location. The controller is configured to control the DUT positioner to rotate the device under test at the test location in azimuth and/or elevation. The controller is configured to control the DUT positioner to rotate the device under test into a first orientation for a first OTA power measurement by a first one of the at least two measurement antennas. The controller is configured to control the DUT positioner to rotate the device under test into a second orientation for a second OTA power measurement by a second one of the at least two measurement antennas. A relative orientation between the device under test in the first orientation and the first one of the at least two measurement antennas is the same as a relative orientation between the device under test in the second orientation and the second one of the at least two measurement antennas. Further, an OTA measurement method for performing OTA measurements on a device under test by an OTA measurement system is described.

A contact probe includes a first plunger, a contact terminal, and a conductive member. The first plunger is contactable with one of an electrode of a semiconductor device and a pad of a test jig. The contact terminal is contactable with the other of the electrode of the semiconductor device and the pad of the test jig. The conductive member covers a part of the first plunger. The conductive member and the first plunger are provided to bring an end portion of the first plunger and the contact terminal into a conduction state when the end portion of the first plunger is pressed by a force smaller than a predetermined force, and bring the end portion of the first plunger and the contact terminal into a nonconduction state when the end portion of the first plunger is pressed by a force equal to or larger than the predetermined force.

A failure pattern obtaining method and apparatus are provided. The method includes that: a chip test result picture for a wafer is obtained, the chip test result picture being marked with a plurality of failure test points; a vector for every two points among all failure test points is calculated; a plurality of failure test points having a same vector are designated as a same group; a plurality of pending failure patterns are separated from each of groups; a failure pattern is obtained based on the plurality of the pending failure patterns.

The invention relates to a contacting module (1) by means of which the individual electrical and optical inputs and outputs (A.sub.oC) of optoelectronic chips (2) are connected to the device-specific electrical and optical inputs and outputs of a test apparatus. It is characterized by a comparatively high adjustment insensitivity of the optical contacts between the chips (2) and the contacting module (1), which is achieved, for example, by technical measures which result in the optical inputs (E.sub.oK) of the chip (2) or on the contacting module (1) being irradiated in every possible adjustment position by the optical signal (S.sub.o) to be coupled in.

A heater substrate has an insulating substrate having a first surface and a second surface on the opposite side relative to the first surface and at least one heating element of spiral shape including plural heater wire pieces and positioned in or on the insulating substrate. The heating element of spiral shape has at least one adjustment section including a turn of all or some of the plural heater wire pieces. The plural heater wire pieces include a first heater wire piece and a second heater wire piece adjacent to the inner side of the first heater wire piece. In the adjustment section, the length of the first heater wire piece is smaller than the length of the second heater wire piece.

Prober for a test system for testing a device under test is disclosed. In one example, the prober comprises a chuck configured for carrying the device under test, a transport circuitry for transporting electric signals to and/or away from the device under test. A cooling unit is directly thermally coupled with the device under test and configured for cooling the device under test at a main surface of the device under test facing the chuck.

Integrating a bracket with planarity adjustment holding a wafer probe securely, with a low-profile impedance tuner that is mounted on a 3-axis tuner positioner under an angle matching the angle of the wafer probe. The low-profile tuner has its tuning probe operating as close as physically possible within the distance of an RF adapter from the wafer-probe and is connected directly with the wafer-probe. This integration offers the maximum possible tuning range, while simultaneously offering planarity (THETA) control. It also eliminates the need for an extension RF cable between the instrument (tuner) and the wafer-probe, including a set of two coaxial adapters.

A test apparatus includes a test chamber in which a plurality of the semiconductor packages having a plurality of component dies is secured, an operation tester configured to conduct an operation test to the plurality of semiconductor packages to detect whether at least one semiconductor package is an operation fault package having a fault and identify a fault package point at which the operation fault package is located, a fault heat detector configured to detect a fault heat generated from the fault, and a test controller configured to control the operation tester to conduct the operation test to the plurality of semiconductor packages and control the fault heat detector subsequent to the operation test to detect the fault heat generated from the fault of the operation fault package to determine a vertical point of the fault and to determine a fault die having the fault.

Probe systems configured to test a device under test and methods of operating the probe systems are disclosed herein. The probe systems include an electromagnetically shielded enclosure, which defines an enclosed volume, and a temperature-controlled chuck, which defines a support surface configured to support a substrate that includes the DUT. The probe systems also include a probe assembly and an optical microscope. The probe systems further include an electromagnet and an electronically controlled positioning assembly. The electronically controlled positioning assembly includes a two-dimensional positioning stage, which is configured to selectively position a positioned assembly along a first two-dimensional positioning axis and also along a second two-dimensional positioning axis. The electronically controlled positioning assembly also includes a first one-dimensional positioning stage that operatively attaches the optical microscope to the positioned assembly and a second one-dimensional positioning stage that operatively attaches the electromagnet to the positioning assembly.

A control part of a semiconductor fault analysis device outputs an alignment command that moves a chuck to a position at which a target is detectable by a first optical detection part and then aligns an optical axis of a second optical system with an optical axis of a first optical system with the target as a reference, and outputs an analysis command that applies a stimulus signal to a semiconductor device and receives light from the semiconductor device emitted according to a stimulus signal with at least one of a first optical detection part and a second optical detection part in a state in which a positional relationship between the optical axis of the first optical system and the optical axis of the second optical system is maintained.