This document describes techniques and systems for leakage screening based on power prediction. In particular, the described systems and techniques estimate, during a silicon manufacturing process, use-case power (e.g., low power, ambient power, high power, gaming power) to apply leakage screening for apart (e.g., a chip package). In some aspects, measurable silicon parameters (e.g., leakage values, bin values, processor sensor values) may be used for use-case power prediction. Using the described techniques, a maximum allowable predicted use-case power can be determined and used for leakage screening regardless of an individual rail leakage or voltage bin assignment.

An image-capturing unit includes: an image-capturing chip; a power supply circuit unit that outputs electrical power to be fed to the image-capturing chip; a power supply line that feeds electrical power from the power supply circuit unit to the image-capturing chip; a disconnecting unit that is provided to the power supply line and is electrically disconnecting the power supply circuit unit and the image-capturing chip when a leakage current of the image-capturing chip is measured; and an implementation substrate on which the power supply circuit unit, the image-capturing chip, the power supply line and the disconnecting unit are implemented.

An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

A current measurement circuit may use a probabilistic technique to determine a current from a circuit block. In one embodiment, the circuit includes a comparator circuit, a first current sensing element (such as a first resistor), and a control circuit. The first current sensing element is coupled to the comparator circuit to establish a first comparator input signal representative of the current at an input of the comparator circuit. The control circuit is coupled to the comparator circuit to obtain a first plurality of comparator output decisions corresponding to the first current sensing element for a specified count, determine a first proportion of comparator output decisions meeting a specified criterion, and determine a voltage value of the first comparator input signal from the first proportion. The control circuit is configured to determine a current value using the voltage value of the first comparator input signal and an impedance value of the first current sensing element. The current measurement circuit is relatively low-cost and easy to implement, without requiring a precision reference voltage, current, and/or high-cost analog-to-digital converters (ADCs).

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

An image-capturing unit includes: an image-capturing chip; a power supply circuit unit that outputs electrical power to be fed to the image-capturing chip; a power supply line that feeds electrical power from the power supply circuit unit to the image-capturing chip; a disconnecting unit that is provided to the power supply line and is electrically disconnecting the power supply circuit unit and the image-capturing chip when a leakage current of the image-capturing chip is measured; and an implementation substrate on which the power supply circuit unit, the image-capturing chip, the power supply line and the disconnecting unit are implemented.

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

An example method provides a power MOSFET, a voltage source coupled to the power MOSFET, and a current measurement device coupled to a first non-control terminal of the power MOSFET. The voltage source, the current measurement device, and a second non-control terminal of the power MOSFET couple to ground. The method uses the voltage source to apply a voltage between a gate terminal and the second non-control terminal of the power MOSFET, the voltage greater than zero volts and less than a threshold voltage of the power MOSFET. The method also uses the current measurement device to measure a first current flowing through the first non-control terminal while applying the voltage. The method further uses the first current to predict a second current through the first non-control terminal for a voltage between the gate terminal and the second non-control terminal that is approximately zero.

A performance testing method for determining a performance of a device under test having non-linear characteristics is disclosed. The performance testing method comprises the following steps: generating a hard clipper model of said device under test; generating a test signal having predefined properties; forwarding said test signal to the device under test, wherein the device under test generates an output signal based on said test signal; feeding said hard clipper model with said test signal, thereby generating a model output signal; and comparing said output signal to said model output signal in order to determine the performance of the device under test. Moreover, a measurement system for determining a performance of a device under test having non-linear characteristics is disclosed.

A field-programmable gate array includes a memory, a firmware state machine, a register, and an interconnect structure. The memory is configured to store a plurality of configurations. Each of the plurality of configurations has at least one parameter associated therewith. The firmware state machine is configured to read the parameters stored in the memory. The register is configured to have the parameters associated with the plurality of configurations written thereto. The interconnect structure is configured to transmit the parameters between the firmware state machine and the register. The interconnect structure is configured to receive the parameters associated with the plurality of the configurations simultaneously and the interconnect structure is configured to transmit the received parameters associated with the plurality of configurations to the register simultaneously.