Systems and methods for detecting defects are disclosed. According to certain embodiments, a method of performing image processing includes acquiring one or more images of a sample, performing first image analysis on the one or more images, identifying a plurality of first features in the one or more images, determining pattern data corresponding to the plurality of first features, selecting at least one of the plurality of first features based on the pattern data, and performing second image analysis of the at least one of the plurality of first features. Methods may also include determining defect probability of the plurality of first features based on the pattern data. Selecting the at least one of the plurality of first features may be based on the defect probability.

Systems and methods for detecting defects are disclosed. According to certain embodiments, a method of performing image processing includes acquiring one or more images of a sample, performing first image analysis on the one or more images, identifying a plurality of first features in the one or more images, determining pattern data corresponding to the plurality of first features, selecting at least one of the plurality of first features based on the pattern data, and performing second image analysis of the at least one of the plurality of first features. Methods may also include determining defect probability of the plurality of first features based on the pattern data. Selecting the at least one of the plurality of first features may be based on the defect probability.

An over-the-air test system is described that is used for testing a device under test in a wireless communication environment. The test system comprises at least one measurement antenna connected with a signal processing unit configured to generate a signal or to analyze a signal. The test system further comprises a reflector configured to reflect electromagnetic signals, the reflector being positioned in a signal path established between the device under test and the measurement antenna such that the signals are reflected by the reflector. The measurement antenna has a radiation pattern with a main lobe, the measurement antenna being configured to adjust the direction of the main lobe with respect to the reflector in order to simulate different impinging angles of the signals. Further, a method for testing a device under test is described.

An over-the-air test system is described that is used for testing a device under test in a wireless communication environment. The test system comprises at least one measurement antenna connected with a signal processing unit configured to generate a signal or to analyze a signal. The test system further comprises a reflector configured to reflect electromagnetic signals, the reflector being positioned in a signal path established between the device under test and the measurement antenna such that the signals are reflected by the reflector. The measurement antenna has a radiation pattern with a main lobe, the measurement antenna being configured to adjust the direction of the main lobe with respect to the reflector in order to simulate different impinging angles of the signals. Further, a method for testing a device under test is described.

A pattern defect detection method capable of detecting a pattern defect of a semiconductor integrated circuit with higher accuracy is disclosed. The pattern defect detection method includes: extracting an image of an inspection target pattern from an image of a specimen; identifying a reference pattern from design data, the reference pattern having the same shape and the same position as those of the inspection target pattern; calculating a brightness index value indicating a brightness of an entirety of the inspection target pattern; repeating said extracting an inspection target pattern, said identifying a reference pattern, and said calculating a brightness index value, thereby building mass data containing brightness index values of inspection target patterns and corresponding reference patterns; determining a standard range of brightness index value based on the brightness index values contained in the mass data; and detecting a defect of the inspection target pattern based on whether or not the calculated brightness index value is within the standard range.

A pattern defect detection method capable of detecting a pattern defect of a semiconductor integrated circuit with higher accuracy is disclosed. The pattern defect detection method includes: extracting an image of an inspection target pattern from an image of a specimen; identifying a reference pattern from design data, the reference pattern having the same shape and the same position as those of the inspection target pattern; calculating a brightness index value indicating a brightness of an entirety of the inspection target pattern; repeating said extracting an inspection target pattern, said identifying a reference pattern, and said calculating a brightness index value, thereby building mass data containing brightness index values of inspection target patterns and corresponding reference patterns; determining a standard range of brightness index value based on the brightness index values contained in the mass data; and detecting a defect of the inspection target pattern based on whether or not the calculated brightness index value is within the standard range.

An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.

A semiconductor storage device of an embodiment includes a stacked body including a plurality of conductive layers stacked via insulating layers, and a step portion in which end portions of the plurality of conductive layers have a stepwise shape, a plurality of pillars extending in the stacked body in a stacking direction of the stacked body, and forming a plurality of memory cells at intersection portions with at least part the plurality of conductive layers, and a plurality of contacts disposed for respective steps of the step portion, and to be electrically connected with the conductive layers of the respective steps. Among the plurality of contacts, a first plug is disposed on a contact connected to an (n1)-th (n is an integer of two or more) conductive layer from an undermost layer, and a second plug is disposed on the first plug, and among the plurality of contacts, the first plug is not disposed but the second plug is disposed on a contact connected to an n-th conductive layer from the undermost layer.

The present invention provides a method for positioning short circuit failure, used to position the short circuit point between a first metal wire and a second metal wire. The positioning method comprises: measuring the resistance between the first metal wire and the second metal wire, and positioning the first region where the short circuit point is located by a resistance ratio. In the first region, the short circuit point may be gradually approached by periodically cutting the first metal wire and the second metal wire, electrically isolating the cut portions, and performing a plurality of voltage contrast analysis on the first metal wire and the second metal wire based on the principle of the dichotomy, thereby accurately locating the short circuit point. With the positioning method provided by the present invention, the region where the short circuit defect of the nA (nano ampere) level is located may be accurately found from the first metal wire and the second metal wire that are extremely long. The present invention contributes to improving the yield of a semiconductor device based on the defect adjustment process.

Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.