Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (NCEM) of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments (DOEs), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

A soft error inspection method for a semiconductor device includes: irradiating and scanning the semiconductor device with a laser beam or an electron beam; and measuring and storing a time of bit inversion for each of areas irradiated with the laser beam or the electron beam of the semiconductor device.

A soft error inspection method for a semiconductor device includes: irradiating and scanning the semiconductor device with a laser beam or an electron beam; and measuring and storing a time of bit inversion for each of areas irradiated with the laser beam or the electron beam of the semiconductor device.

A system for monitoring and identifying states of a semiconductor device, the system including at least one acoustic sensor for sensing acoustic emission emitted by at least one semiconductor device operating at a voltage of less than or equal to 220 V, the at least one acoustic sensor outputting at least one acoustic emission signal and a signal processing unit for receiving the at least one acoustic emission signal from the at least one acoustic sensor and for analyzing the at least one acoustic emission signal, the signal processing unit providing an output based on the analyzing, the output being indicative at least of whether the at least one semiconductor device is in an abnormal operating state with respect to a normal operating state of the semiconductor device.

A voltage contrast imaging defect detection system includes a voltage contrast imaging tool and a controller coupled to the voltage contrast imaging tool. The controller is configured to generate one or more voltage contrast imaging metrics for one or more structures on a sample, determine one or more target areas on the sample based on the one or more voltage contrast imaging metrics, receive a voltage contrast imaging dataset for the one or more target areas on the sample from the voltage contrast imaging tool, and detect one or more defects based on the voltage contrast imaging dataset.

A voltage contrast imaging defect detection system includes a voltage contrast imaging tool and a controller coupled to the voltage contrast imaging tool. The controller is configured to generate one or more voltage contrast imaging metrics for one or more structures on a sample, determine one or more target areas on the sample based on the one or more voltage contrast imaging metrics, receive a voltage contrast imaging dataset for the one or more target areas on the sample from the voltage contrast imaging tool, and detect one or more defects based on the voltage contrast imaging dataset.

Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

Defect information obtained from a test wafer is received. The test wafer was fabricated according to an Integrated Circuit (IC) design layout. A plurality of first regions of interest (ROIs) is received based on the defect information. The first ROIs each correspond to a region of the IC design layout where a wafer defect has occurred. A frequency domain analysis is performed for the first ROIs. A wafer defect probability is forecast for the IC design layout based at least in part on the frequency domain analysis.

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for an enclosure, which may be referred to as a cartridge, that surrounds a semiconductor device prior to the semiconductor device being bombarded with an electron beam during operational testing. In embodiments, the enclosure may include a cooling plate that includes a thermal cooling mechanism that is thermally coupled with the semiconductor device to control the temperature of the semiconductor device during testing. The thermal cooling mechanism may include a manifold that extends through the plate through which a cooled fluid, cooled air, or some other cool material may be circulated to cool the semiconductor device. Other embodiments may be described and/or claimed.

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for an enclosure, which may be referred to as a cartridge, that surrounds a semiconductor device prior to the semiconductor device being bombarded with an electron beam during operational testing. In embodiments, the enclosure may include a cooling plate that includes a thermal cooling mechanism that is thermally coupled with the semiconductor device to control the temperature of the semiconductor device during testing. The thermal cooling mechanism may include a manifold that extends through the plate through which a cooled fluid, cooled air, or some other cool material may be circulated to cool the semiconductor device. Other embodiments may be described and/or claimed.