Patent classifications
G01R31/309
Immunity Evaluation System and Immunity Evaluation Method
Provided is an immunity evaluation system that enables design feedback in consideration of a subject wiring and an improvement amount for improving an electromagnetic noise resistance of a circuit board. An immunity evaluation device includes: a storage unit configured to store characteristic data including probe-circuit board wiring coupling characteristics which are determined by a combination of a near-field probe and circuit board characteristics, and a test result; and an IC reaching signal level estimation unit configured to estimate a signal level reaching a terminal of an evaluation target IC. The immunity evaluation device receives board design information, information of the near-field probe, and test waveform instruction information of a signal applied to the near-field probe. The IC reaching signal level estimation unit reads the coupling characteristics from the storage unit based on the board design information of a test subject circuit board and the information of the near-field probe, and outputs a value of the IC reaching signal level reaching a terminal of the evaluation target IC from the board design information of the test subject circuit board, the information of the near-field probe, and the coupling characteristics.
Immunity Evaluation System and Immunity Evaluation Method
Provided is an immunity evaluation system that enables design feedback in consideration of a subject wiring and an improvement amount for improving an electromagnetic noise resistance of a circuit board. An immunity evaluation device includes: a storage unit configured to store characteristic data including probe-circuit board wiring coupling characteristics which are determined by a combination of a near-field probe and circuit board characteristics, and a test result; and an IC reaching signal level estimation unit configured to estimate a signal level reaching a terminal of an evaluation target IC. The immunity evaluation device receives board design information, information of the near-field probe, and test waveform instruction information of a signal applied to the near-field probe. The IC reaching signal level estimation unit reads the coupling characteristics from the storage unit based on the board design information of a test subject circuit board and the information of the near-field probe, and outputs a value of the IC reaching signal level reaching a terminal of the evaluation target IC from the board design information of the test subject circuit board, the information of the near-field probe, and the coupling characteristics.
Integrated photonic test circuit
A photonic circuit testing device, including a photonic test chip including, on the side of a first surface of the chip: micropillars, each intended to be placed in contact with a corresponding electric connection pad of the photonic circuit; and first optical input/output ports, each intended to be optically coupled to a second corresponding optical input/output port of the photonic circuit.
Integrated photonic test circuit
A photonic circuit testing device, including a photonic test chip including, on the side of a first surface of the chip: micropillars, each intended to be placed in contact with a corresponding electric connection pad of the photonic circuit; and first optical input/output ports, each intended to be optically coupled to a second corresponding optical input/output port of the photonic circuit.
Measurement models of nanowire semiconductor structures based on re-useable sub-structures
Methods and systems for generating measurement models of nanowire based semiconductor structures based on re-useable, parametric models are presented herein. Metrology systems employing these models are configured to measure structural and material characteristics (e.g., material composition, dimensional characteristics of structures and films, etc.) associated with nanowire semiconductor fabrication processes. The re-useable, parametric models of nanowire based semiconductor structures enable measurement model generation that is substantially simpler, less error prone, and more accurate. As a result, time to useful measurement results is significantly reduced, particularly when modelling complex, nanowire based structures. The re-useable, parametric models of nanowire based semiconductor structures are useful for generating measurement models for both optical metrology and x-ray metrology, including soft x-ray metrology and hard x-ray metrology.
Measurement models of nanowire semiconductor structures based on re-useable sub-structures
Methods and systems for generating measurement models of nanowire based semiconductor structures based on re-useable, parametric models are presented herein. Metrology systems employing these models are configured to measure structural and material characteristics (e.g., material composition, dimensional characteristics of structures and films, etc.) associated with nanowire semiconductor fabrication processes. The re-useable, parametric models of nanowire based semiconductor structures enable measurement model generation that is substantially simpler, less error prone, and more accurate. As a result, time to useful measurement results is significantly reduced, particularly when modelling complex, nanowire based structures. The re-useable, parametric models of nanowire based semiconductor structures are useful for generating measurement models for both optical metrology and x-ray metrology, including soft x-ray metrology and hard x-ray metrology.
METHOD, METHOD OF INSPECTING MAGNETIC DISK DEVICE, AND ELECTRONIC COMPONENT
According to one embodiment, a method includes: supplying electrical energy to a first path by an inspection circuit with a short circuit between two first terminals through a first probe; and detecting an electrical characteristic on the first path by the inspection circuit when the electrical energy is supplied to the first path. The two first terminals are included in a plurality of second terminals included in a flexible printed circuit board. The flexible printed circuit board includes: an electronic component including the inspection circuit and a plurality of third terminals; the plurality of second terminals; and a plurality of first wired lines connecting the plurality of second terminals and the plurality of third terminals. The first path is formed by: the two first terminals; two second wired lines connected to the two first terminals among the plurality of first wired lines; and two fourth terminals connected to the two second wired lines among the plurality of third terminals.
METHOD, METHOD OF INSPECTING MAGNETIC DISK DEVICE, AND ELECTRONIC COMPONENT
According to one embodiment, a method includes: supplying electrical energy to a first path by an inspection circuit with a short circuit between two first terminals through a first probe; and detecting an electrical characteristic on the first path by the inspection circuit when the electrical energy is supplied to the first path. The two first terminals are included in a plurality of second terminals included in a flexible printed circuit board. The flexible printed circuit board includes: an electronic component including the inspection circuit and a plurality of third terminals; the plurality of second terminals; and a plurality of first wired lines connecting the plurality of second terminals and the plurality of third terminals. The first path is formed by: the two first terminals; two second wired lines connected to the two first terminals among the plurality of first wired lines; and two fourth terminals connected to the two second wired lines among the plurality of third terminals.
Method of testing an interconnection substrate and apparatus for performing the same
In a method of testing an interconnection substrate, a blocking condition of a reference light reflected from a probe having an intrinsic optical characteristic may be set. An electric field emitted from a test interconnection substrate having a plurality of circuits may change the intrinsic optical characteristics of the probe into test optical characteristics. Light may be irradiated to the probe having the test optical characteristics. The reference light reflected from the probe having the test optical characteristic may be blocked in accordance with the blocking condition. The remaining reflected light that may be due to an abnormal circuit may be detected.
HIGH PRECISION OPTICAL CHARACTERIZATION OF CARRIER TRANSPORT PROPERTIES IN SEMICONDUCTORS
A precise optical technique for measuring electronic transport properties in semiconductors is disclosed. Using tightly focused laser beams in a photo-modulated reflectance system, the modulated reflectance signal is measured as a function of the longitudinal (Z) displacement of the sample from focus. The modulated component of the reflected probe beam is a Gaussian beam with its profile determined by the focal parameters and the complex diffusion length. The reflected probe beam is collected and input to the detector, thereby integrating over the radial profile of the beam. This results in a simple analytic expression for the Z dependence of the signal in terms of the complex diffusion length. Best fit values for the diffusion length and recombination lifetime are obtained via a nonlinear regression analysis. The output diffusion lengths and recombination lifetimes and their estimated uncertainties may then be used to evaluate various transport properties and their associated uncertainties.