The semiconductor failure analysis device includes: a light source configured to generate irradiation light with which the semiconductor device is irradiated; a solid immersion lens disposed on an optical path of the irradiation light; a light detection unit configured to receive reflected light and to output a detection signal according to the reflected light; an optical system 6 disposed between the light source and the solid immersion lens to emit the irradiation light to the semiconductor device via the solid immersion lens and disposed between the solid immersion lens and the light detection unit to emit the reflected light received via the solid immersion lens to the light detection unit. The light source emits the irradiation light having a center wavelength of 880 nm or more and 980 nm or less. The solid immersion lens is formed of GaAs.

The invention relates to a contacting module (1) by means of which the individual electrical and optical inputs and outputs (A.sub.oC) of optoelectronic chips (2) are connected to the device-specific electrical and optical inputs and outputs of a test apparatus. It is characterized by a comparatively high adjustment insensitivity of the optical contacts between the chips (2) and the contacting module (1), which is achieved, for example, by technical measures which result in the optical inputs (E.sub.oK) of the chip (2) or on the contacting module (1) being irradiated in every possible adjustment position by the optical signal (S.sub.o) to be coupled in.

The invention relates to a contacting module (1) by means of which the individual electrical and optical inputs and outputs (A.sub.oC) of optoelectronic chips (2) are connected to the device-specific electrical and optical inputs and outputs of a test apparatus. It is characterized by a comparatively high adjustment insensitivity of the optical contacts between the chips (2) and the contacting module (1), which is achieved, for example, by technical measures which result in the optical inputs (E.sub.oK) of the chip (2) or on the contacting module (1) being irradiated in every possible adjustment position by the optical signal (S.sub.o) to be coupled in.

A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. Updating the time-dependent map of the emissions based on variable dwell times at respective locations of the DUT.

A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. Updating the time-dependent map of the emissions based on variable dwell times at respective locations of the DUT.

A circuit board inspection apparatus includes an inspection processing portion that inspects an electric circuit of a board to be inspected, an inspection jig, and a position detector used to position the inspection processing portion relative to the board to be inspected. The inspection jig includes a probe unit having a probe, a first board, a second board located in parallel with the first board in a thickness direction of the first board, an electrical connection portion that electrically connects the first board and the second board, and a second board holding portion that holds the second board from the first board and holds the probe unit on a side opposite to the first board side. The second board holding portion has a position detection opening penetrating in the thickness direction, at a position overlapping the position detector as viewed from the thickness direction of the second board holding portion.

A test apparatus and method for testing a semiconductor device. The semiconductor device includes an integrated circuit and a plurality of external radiating elements located at a surface of the device. The external radiating elements include at least one transmit element and receive element. The test apparatus includes a plunger. The plunger includes a dielectric portion having a surface for placing against the surface of the device. The plunger also includes at least one waveguide. Each waveguide extends through the plunger for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the device. The dielectric portion is configured to provide a matched interface for the electromagnetic coupling of the waveguide openings to the plurality of external radiating elements of the device.

A test apparatus and method for testing a semiconductor device. The semiconductor device includes an integrated circuit and a plurality of external radiating elements located at a surface of the device. The external radiating elements include at least one transmit element and receive element. The test apparatus includes a plunger. The plunger includes a dielectric portion having a surface for placing against the surface of the device. The plunger also includes at least one waveguide. Each waveguide extends through the plunger for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the device. The dielectric portion is configured to provide a matched interface for the electromagnetic coupling of the waveguide openings to the plurality of external radiating elements of the device.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.