A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

A test and measurement device includes an input for receiving a test waveform from a Device Under Test (DUT), where the test waveform has a plurality of input level transitions, a selector structured to respectively and individually extract only those portions of the test waveform that match two or more predefined patterns of input level transitions of the test waveform, a noise compensator structured to individually determine and remove, for each of the extracted portions of the waveform, a component of a jitter measurement caused by random noise of the test and measurement device receiving the test waveform, a summer structured to produce a composite distribution of timing measurements with removed noise components from the extracted portions of the test waveform, and a jitter processor structured to determine a first noise-compensated jitter measurement of the DUT from the composite distribution. Methods of determining noise-compensated jitter measurements are also disclosed.

In a particular implementation, a method to reduce noise/clock jitter and to generate a “stretched” output clock to optimize for jitter of the output clock is disclosed. The method includes: generating two or more clock phases upon detecting a transient voltage by a detector circuit, generating an output clock signal based on one of the two or more clock phases; and altering a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.

An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

A method and system measure a characteristic of a signal under test (SUT) using a signal measurement device. The method includes receiving and digitizing the first and second copies of the SUT through first and second input channels to obtain first and second digitized waveforms; repeatedly determining measurement values of the SUT characteristic in the first and second digitized waveforms to obtain first and second measurement values, which are paired in measurement value pairs; multiplying the first and second measurement values in each of the measurement value pairs to obtain measurement products; determining an average value of the measurement products to obtain an MSV of the measured SUT characteristic; and determine a square root of the MSV to obtain an RMS value of the measured SUT characteristic. The RMS value substantially omits variations not in the SUT, which are introduced by only one of the first and second input channels.

A method of operating a data processing system to generate a jitter-injected signal from an input signal that is a function of time is disclosed. A time offset corresponding to a first time is generated according to a jitter specification that specifies the offset as a function of time. The jitter-injected signal at the first time is generated by evaluating the input signal at a time equal to a sum of the time offset and the first time. If the jitter specification only provides offsets at signal crossing times, interpolation is used to derive time offsets at non-signal crossing times.

A measurement is made of jitter present in a jittery clock signal. A digital sinusoid generator circuit clocked by the jittery clock signal generates a pulse density modulation (PDM) signal corresponding to a sinusoid waveform. The PDM signal is converted by a sigma-delta modulator circuit to an oscillating frequency signal with an output of digital values digital values indicative of oscillating frequency signal phase. Responsive to the jittery clock signal, the digital values indicative of oscillating frequency signal phase are sampled. A digital differentiator circuit determines a digital difference between consecutive samples of the digital values indicative of oscillating frequency signal phase. The digital difference is processed by a digital signal processing circuit to generate a frequency spectrum and determine from signal-to-noise ratio a measurement of jitter in the jittery clock signal.

A jitter measuring setup (10) comprises a signal generator (14), a sample-and-hold circuit (15), and the inventive all stochastic jitter measuring device (1) comprising signal acquisition means (2) and calculation means (3). The input signal of the sample-and-hold circuit (15) is generated by the signal generator (14). Furthermore, the output signal of the sample-and-hold circuit (15), respectively the input signal of the measuring device (1), is comprised of a superposition of the sampled input signal of the sample-and-hold circuit (15) and a cyclostationary random process.

A method measures a characteristic of a SUT using a signal measurement device having multiple input channels. The method includes digitizing first and second copies of the SUT in first and second input channels to obtain first and second digitized waveforms; repeatedly determining measurement values of the SUT characteristic in the first and second digitized waveforms to obtain first and second measurement values, respectively, each second measurement value being paired with a first measurement value to obtain measurement value pairs; multiplying the first and second measurement values in each of the measurement value pairs to obtain measurement products; determining a mean-squared value (MSV) of the SUT characteristic measurement; and determining a square root of the MSV to obtain a root-mean-squared (RMS) value of the measured SUT characteristic, which substantially omits variations not in the SUT, which are introduced by only one of the first or second input channel.

A time and frequency domain signal conditioning device including one or more signal terminals, one or more rails, and a passive signal conditioning means for reducing a switching noise jitter signature present in an output signal of a feedback control loop circuitry with a plurality of noise carrying jittering ramps is disclosed. The passive signal conditioning means including the rails is characterized by a set of specified characteristics to condition pre-existing noise amplitude and slopes of the output signal such that the conditioned output signal cooperates with the feedback control loop circuitry. As a consequence the switching noise jitter signature which is produced by transient noise displacement or noise perturbation in the time domain when the output signal jitters can be reduced in the output of the feedback control loop circuitry.