A semiconductor system may include a first semiconductor device configured to output a clock, receive and output data, and detect a jitter of a transmission path according to a level combination of a plurality of monitoring signals. The semiconductor system may also include a second semiconductor device configured to generate the plurality of monitoring signals of which the level combination is changed according to phase differences between an internal clock generated through the transmission path for transmitting the clock and a plurality of divided clocks obtained by dividing the frequency of the clock.

A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope

A load pull system for making measurements on a DUT at millimeter wave frequencies using active tuning. The system uses phase and amplitude control of each signal at low frequency before being upconverted to the millimeter wave measurement frequencies. The measured signals at the DUT plane may be down-converted for measurement with a low frequency analyzer.

A circuit includes: a first delay circuit configured to receive a first clock signal; a second delay circuit configured to receive a second clock signal; a delay control circuit, coupled to the first and second delay circuits, and configured to cause the first and second delay circuits to respectively align the first and second clock signals within a noise window; and a loop control circuit, coupled to the first and second delay circuits, and configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits so as to determine the noise window.

A signal analysis method is disclosed. The method comprises the following steps: An input signal comprising a symbol sequence is received, wherein the input signal is associated with a first clock signal comprising at least one jitter component. A second clock signal is recovered based on said input signal. At least one jitter parameter is determined that is associated with said at least one jitter component. A jitter signal is reconstructed based on said at least one jitter parameter, wherein said jitter signal is associated with said at least one jitter component. A third clock signal is determined based on said second clock signal and said jitter signal. Further, a measurement instrument is disclosed.

An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).

A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.

Various examples relate to apparatuses, methods, and computer programs for executing an executable, and to a method for distributing software or firmware. An apparatus for executing an executable comprises interface circuitry, machine-readable instructions, and processing circuitry for executing the machine-readable instructions to identify, for the executable, a trigger to activate or deactivate a noise injection mode during execution of the executable, the noise injection mode being suitable for introducing noise during execution of the executable, and activate or deactivate the noise injection mode based on the identified trigger.

An apparatus and method for analyzing phase noise in a signal. A plurality of signal samples, each signal sample representing a value of phase noise in a signal-under-test at a corresponding offset frequency, and filter data representing filter characteristics on a first side of a spectrum boundary, are used to derive filtered signal samples. A measure of noise is derived from the filtered signal samples. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

A method for estimating jitter of a clock-signal-under-test includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method includes generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the phase-adjusted clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter estimate using an estimated standard deviation of a distribution of edges of the clock signal based on the N digital time codes for each of the P phase adjustments.