A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

An apparatus for determining an eye mask of a device under test (DUT) which is configured to receive a data bit stream signal including a threshold level value and output a data bit stream output signal. The apparatus includes an input unit configured to receive the data bit stream output signal provided by the DUT, an evaluation unit configured to evaluate the received data bit output signal and provide an evaluation result, and a controller configured to change the threshold level value in response to the evaluation result. The apparatus is integrated into the DUT and can operates autonomously without multiple interactions with a tester.

According to some embodiments, a tester tests one or more DUTs by utilizing one or more respective reference devices. The tester comprises one or more test sites and one or more test circuits operatively coupled to each of the test sites. Each test site is configured to: hold a reference device and a DUT, transmit a transmitted electromagnetic RF signal including a test data pattern to the DUT, and receive a received electromagnetic RF signal emitted from the DUT. The test circuits are configured to: receive a first electrical signal converted from the received electromagnetic RF signal, extract first data from the first electrical signal, determine a first error rate between the test data pattern and the first data, and generate a test result on the basis of the first error rate.

A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

A test instrument may include a transmitter configured to transmit signals to a unit under test, a receiver configured to receive signals from the unit under test, and a controller configured to generate a transmitter compensation filter by (i) transmitting, with the transmitter, complex multi-sine signals over a first plurality of observed frequencies within a predetermined baseband frequency range, (ii) estimating a first plurality of frequency responses that compensate for in-phase and quadrature (IQ) imbalance at the first plurality of observed frequencies within the predetermined baseband frequency range, and (iii) determining, using the first plurality of frequency responses, a transmitter polynomial surface, and to compensate, using the transmitter compensation filter, at least one of the signals to be transmitted by the transmitter to reduce IQ imbalance in the transmitted signals, including using the transmitter polynomial surface to calculate a frequency response that reduces the IQ imbalance in the transmitted signals.

Technologies and techniques for monitoring the reliability of an electronic system having one or more electronic components. A transmission quality of signals transmitted to or from the electronic system over a wired electrical signal transmission path are measured at different measurement times and according to a predetermined transmission quality measure. For each of the measurement times, the associated measured transmission quality is compared with a respective associated transmission quality reference value previously determined according to the transmission quality measure. A value of a reliability indicator associated with the respective measurement time is determined in dependence on the result of the associated comparison. In this regard, the transmission quality measure may be defined as a measure of the extent of a subrange of a one- or multi-dimensional operating parameter range of the electronic system in which, according to a predetermined reliability criterion, the electronic system operates reliably.

A signal generator includes inverse characteristic calculation means for calculating an inverse characteristic of a transfer function from an inverse characteristic of a frequency characteristic of a signal based on the transmission standard, inverse Fourier transform means for calculating impulse responses of a plurality of points by performing inverse Fourier transform on the inverse characteristic of the transfer function, impulse response cutout means for cutting out the points for a predetermined number of taps from the impulse response, frequency characteristic calculation means for calculating a frequency characteristic based on values of the points for the number of taps cut out from the impulse response, and display control means for displaying on a display screen, the frequency characteristic calculated by the frequency characteristic calculation means and an ideal frequency characteristic read from an S parameter file of a device under test.

A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

According to some embodiments, a tester tests one or more DUTs by utilizing one or more respective reference devices. The tester comprises one or more test sites and one or more test circuits operatively coupled to each of the test sites. Each test site is configured to: hold a reference device and a DUT, transmit a transmitted electromagnetic RF signal including a test data pattern to the DUT, and receive a received electromagnetic RF signal emitted from the DUT. The test circuits are configured to: receive a first electrical signal converted from the received electromagnetic RF signal, extract first data from the first electrical signal, determine a first error rate between the test data pattern and the first data, and generate a test result on the basis of the first error rate.

An apparatus for performing an electrical test at a device is described. In one general implementation, an apparatus may include a memory, a receiver, and a processor. The receiver is configured to receive a test signal, convert the test signal into a digital test signal (bit stream) and store the digital test signal in the memory. The receiver identifies when a pre-defined number of bits of the bit stream are available in the memory. The processor is configured to perform a logic operation on the bit stream and a reference signal, generate a test result based on the logic operation, and determine whether the test result satisfies a condition. In some implementations, the processor may be configured to synchronize the digital test signal with the reference signal prior to performing of the logic operation.