A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

An apparatus for determining an eye mask of a device under test (DUT) which is configured to receive a data bit stream signal including a threshold level value and output a data bit stream output signal. The apparatus includes an input unit configured to receive the data bit stream output signal provided by the DUT, an evaluation unit configured to evaluate the received data bit output signal and provide an evaluation result, and a controller configured to change the threshold level value in response to the evaluation result. The apparatus is integrated into the DUT and can operates autonomously without multiple interactions with a tester.

An eye pattern generator for generating an eye pattern of an input signal is provided. The eye pattern generator includes first and second comparators and a control circuit. The first comparator receives the input signal, a clock signal, and a first voltage and compares the input signal with the first voltage according to the clock signal to generate a first comparison signal. The second comparator receives the input signal, the clock signal, and a second voltage lower than the first voltage and compares the input signal with the second voltage according to the clock signal to generate a second comparison signal. The control circuit changes at least one of a level of the first voltage and a level of the second voltage according to the first and second comparison signals to form a region boundary between an open-eye region and a closed-eye region of the eye pattern.

A measurement device comprising a measurement unit adapted to measure a transmission characteristic for providing an eye pattern; and a conversion unit adapted to convert automatically the eye pattern into a character separated values, CSV, file.

According to some embodiments, a tester tests one or more DUTs by utilizing one or more respective reference devices. The tester comprises one or more test sites and one or more test circuits operatively coupled to each of the test sites. Each test site is configured to: hold a reference device and a DUT, transmit a transmitted electromagnetic RF signal including a test data pattern to the DUT, and receive a received electromagnetic RF signal emitted from the DUT. The test circuits are configured to: receive a first electrical signal converted from the received electromagnetic RF signal, extract first data from the first electrical signal, determine a first error rate between the test data pattern and the first data, and generate a test result on the basis of the first error rate.

An eye pattern generator for generating an eye pattern of an input signal is provided. The eye pattern generator includes first and second comparators and a control circuit. The first comparator receives the input signal, a clock signal, and a first voltage and compares the input signal with the first voltage according to the clock signal to generate a first comparison signal. The second comparator receives the input signal, the clock signal, and a second voltage lower than the first voltage and compares the input signal with the second voltage according to the clock signal to generate a second comparison signal. The control circuit changes at least one of a level of the first voltage and a level of the second voltage according to the first and second comparison signals to form a region boundary between an open-eye region and a closed-eye region of the eye pattern.

A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

Embodiments of the present disclosure are directed to an integrated circuit with photonic bit-corrector circuits. The integrated circuit includes a photonic circuit, a photonic bit-corrector circuit, a photodetector array coupled to the photonic bit-corrector circuit, and an electronic circuit coupled to the photodetector array. The photonic circuit includes a plurality of cascaded photonic gates configured to generate a first photonic output signal for a set of photonic input signals applied to the photonic circuit. The photonic bit-corrector circuit is configured to generate a second photonic output signal for the set of photonic input signals applied to the photonic bit-corrector circuit. The photodetector array is configured to generate an electrical signal based on the second photonic output signal. The electronic circuit is configured to compare the electrical signal with a label signal and output a corrected version of the first photonic output signal based on the comparison.

Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.