A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

A waveform observation system includes two communication nodes, a waveform observation apparatus, and a signal generation portion. The two communication nodes execute a full-duplex communication by a differential signal through a transmission line. The waveform observation apparatus observes a communication signal waveform in the transmission line in response to an input of a trigger signal. The signal generation portion outputs the trigger signal. One of the two communication nodes generates a clock signal, and transmits a signal in synchronization with the clock signal. Remaining one of the two communication nodes reproduces the clock signal included in the signal received from the one of the two communication nodes, and transmits a signal in synchronization with the clock signal that is reproduced. The signal generation portion outputs the trigger signal when equal to or more than two symbols indicated by the signal output to the transmission line consecutively coincide with one another.

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

A waveform observation system includes two communication nodes, a waveform observation apparatus, and a signal generation portion. The two communication nodes execute a full-duplex communication by a differential signal through a transmission line. The waveform observation apparatus observes a communication signal waveform in the transmission line in response to an input of a trigger signal. The signal generation portion outputs the trigger signal. One of the two communication nodes generates a clock signal, and transmits a signal in synchronization with the clock signal. Remaining one of the two communication nodes reproduces the clock signal included in the signal received from the one of the two communication nodes, and transmits a signal in synchronization with the clock signal that is reproduced. The signal generation portion outputs the trigger signal when equal to or more than two symbols indicated by the signal output to the transmission line consecutively coincide with one another.

A test and measurement device for determining types of jitter, the test and measurement instrument including an input for receiving an input signal, a converter coupled to the input and structured to generate a spectral power signal for non-deterministic jitter from the received input signal, a threshold detector structured to identify ranges of the spectral power signal that are in excess of a threshold, a filter structured to filter the identified ranges of the spectral power signal, a Gaussian detector structured to determine whether the filtered ranges of the spectral power signal contain primarily Gaussian or non-Gaussian jitter, and a Q-scale analyzer structured to perform further signal analysis only if the Gaussian detector determined that the jitter in the filtered ranges of the spectral power signal contains a mixture of Gaussian and non-Gaussian jitter.

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.