A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

The method of setting the evaluation standard of a semiconductor wafer includes setting the A and B on the basis of an abnormal substances overlooking rate a specific to the light-scattering type surface inspection apparatus specified by an apparatus-induced abnormal substances overlooking rate due to the light-scattering type surface inspection apparatus and a probabilistic abnormal substances overlooking rate, in which A is the number of times of inspection, B is an abnormal substances detection threshold, the apparatus-induced abnormal substances overlooking rate is higher as the target abnormal substances size to be detected is smaller, and the probabilistic abnormal substances overlooking rate is lower as the number of times of inspection increases.

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

A method of analyzing an electrical circuit applied for an electrical system is disclosed. The method includes steps of obtaining a loss parameter and an eye diagram of a circuit channel of the electrical system; comparing the eye diagram with a standard eye diagram to generate a comparison result; generating an analytic result of the loss parameter according to the comparison result in order to adjust the eye diagram; and adjusting the loss parameter according to the analytic result.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

In described examples of a device with built-in-self-test, a multiplexer has at least first and second input terminals and is coupled to receive a first input signal at the first input terminal, a second input signal at the second input terminal, and selection signals. Also, the multiplexer is coupled to output: the first input signal in response to a first combination of the selection signals; the second input signal in response to a second combination of the selection signals; and an analog summation of the first and second input signals in response to a third combination of the selection signals.

The method of setting the evaluation standard of a semiconductor wafer includes setting the A and B on the basis of an abnormal substances overlooking rate a specific to the light-scattering type surface inspection apparatus specified by an apparatus-induced abnormal substances overlooking rate due to the light-scattering type surface inspection apparatus and a probabilistic abnormal substances overlooking rate, in which A is the number of times of inspection, B is an abnormal substances detection threshold, the apparatus-induced abnormal substances overlooking rate is higher as the target abnormal substances size to be detected is smaller, and the probabilistic abnormal substances overlooking rate is lower as the number of times of inspection increases.

A test and measurement system includes a machine learning system, a test and measurement device including a port configured to connect the test and measurement device to a device under test (DUT), and one or more processors, configured to execute code that causes the one or more processors to: acquire a waveform from the device under test (DUT), transform the waveform into a composite waveform image, and send the composite waveform image to the machine learning system to obtain a bit error ratio (BER) value for the DUT. A method of determining a bit error ratio for a device under test (DUT), includes acquiring one or more waveforms from the DUT, transforming the one or more waveforms into a composite waveform image, and sending the composite waveform image to a machine learning system to obtain a bit error ratio (BER) value for the DUT.

In described examples of a device with built-in-self-test, a multiplexer has at least first and second input terminals and is coupled to receive a first input signal at the first input terminal, a second input signal at the second input terminal, and selection signals. Also, the multiplexer is coupled to output: the first input signal in response to a first combination of the selection signals; the second input signal in response to a second combination of the selection signals; and an analog summation of the first and second input signals in response to a third combination of the selection signals.

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.