Methods, systems and techniques are provided to authenticate a device under test (DUT)/system under test (SUT) comprising an electronic component(s). A profile is defined by injecting a signal to elicit an output that is responsive a physical characteristic of the type of DUT/SUT. In respective embodiments the injected signal is defined to elicit an output for time-domain or frequency-domain evaluation. An injected signal may comprise combinations of (non-destructive/non-activating) signals applied to multiple access points for measurement at arbitrary access points of the DUT/SUT. In an embodiment, measurements of multiple DUT/SUTs of a same type are used to define a common profile. In an embodiment, the profile is built using machine learning to define a classifier. In other embodiments, statistical profiles are defined. During use, output is generated for a target DUT/SUT for evaluation relative to the profile. Counterfeit/alternate designs, altered designs, and implants are detectable.

Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

A test and measurement device includes an input for receiving a test waveform from a Device Under Test (DUT), where the test waveform has a plurality of input level transitions, a selector structured to respectively and individually extract only those portions of the test waveform that match two or more predefined patterns of input level transitions of the test waveform, a noise compensator structured to individually determine and remove, for each of the extracted portions of the waveform, a component of a jitter measurement caused by random noise of the test and measurement device receiving the test waveform, a summer structured to produce a composite distribution of timing measurements with removed noise components from the extracted portions of the test waveform, and a jitter processor structured to determine a first noise-compensated jitter measurement of the DUT from the composite distribution. Methods of determining noise-compensated jitter measurements are also disclosed.

A monitoring circuit and a method for function monitoring is disclosed where the device includes the input being connected with a first subassembly that detects a frequency range of the status signal, with the first subassembly being connected with a second subassembly to implement a logical signal combination. The second subassembly is connected with a third subassembly generating a delayed output signal. The method compares a frequency fsw of the status signal with a lower first cutoff frequency f1 and an upper second cutoff frequency f2. When the frequency fsw of the status signal is located within the predetermined frequency range, the functional reliability signal is provided with a first voltage level, and when the frequency fsw of the status signal is located outside of the predetermined frequency range, the functional reliability signal is provided with a second voltage level that is different from the first voltage level.

The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

A multi-die integrated circuit uses an on-chip test distribution module to distribute test data to different dies, such as processor chiplets. The test distribution module receives test input data from an external source via one or more integrated circuit pins and distributes the test input data to the different dies, such that the different dies are able to concurrently apply the test data to one or more circuits. Based on application of the test input data the different dies concurrently generate corresponding test results that are used to identify and address design or operation errors at the dies.

Aspects of the present disclosure are directed to methods, apparatuses and systems involving a switched probe contact. According to an example embodiment, an apparatus includes logic circuitry, a first circuit to communicate signals with the logic circuitry, and a first bond pad connected to the first circuit via a first circuit path. The apparatus also includes a second circuit to communicate signals with the logic circuitry, and a second bond pad connected to the second circuit via a second circuit path. A probe contact is connected to the first bond pad and communicates signals with an external probe, and a switch circuit is connected to the probe contact and the second circuit path. The switch circuit communicates signals between the probe contact and the second circuit path by selectively connecting and disconnecting the probe contact to the second circuit path.

A probe tip module includes a probe tip interface and a probe tip memory. The probe tip interface is connectable to a probe main module. A reduced characterization data set is stored in the probe tip memory. The prove tip module may be part of a probe system or a measurement system.