A server Joint Test Action Group (JTAG) component adaptive interconnection system and method. The system includes a JTAG master device, a programmable device, and a plurality of JTAG components. The programmable device is configured to simulate JTAG timing according to a JTAG protocol and test JTAG channels of the JTAG components connected to the programmable device one by one. The programmable device connects in series a Test Data Output (TDO) signal of a previous JTAG component with a Test Data Input (TDI) signal of a next JTAG component in the programmable device, connects a TDI signal of a first JTAG component with a TDI signal of the JTAG master device, and connects a TDO signal of a last JTAG component with a TDO signal of the JTAG master device, so as to form a JTAG interconnection chain.

An apparatus for electrically coupling an electrical interface of a unit under test with a debugging component includes a bracket assembly having a socket configured to electrically couple with the electrical interface, a baseplate assembly configured to secure the unit under test on a plate, a crane assembly coupled to the bracket assembly, and a cable assembly. The crane assembly is configured to enable movement of the socket relative to the electrical interface in each of a horizontal direction, a vertical direction, and an angular direction; and secure the socket in place relative to the electrical interface while applying a force by the socket against the electrical interface. The cable assembly is associated in part with the bracket assembly and is configured to electrically couple with the socket at a first end and with the debugging component at a second end.

A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.

A testing apparatus comprises a test interface board comprising a plurality of socket interface boards, wherein each socket interface board comprises: a) an open socket to hold a DUT; b) a discrete active thermal interposer comprising thermal properties and operable to make thermal contact with the DUT; c) a superstructure operable to contain the discrete active thermal interposer; and d) an actuation mechanism operable to provide a contact force to bring the discrete active thermal interposer in contact with the DUT.

A semiconductor device, for example an integrated circuit such as a microcontroller (MCU) or a digital signal processor (DSP), includes a semiconductor die coupled with a power supply line, a debug module coupled with the semiconductor die to exchange semiconductor die debug command and data signals with the semiconductor die, and a modem coupled with the power supply line. The debug module is arranged to convey the semiconductor die debug command and data signals over the power supply line.

The present invention relates to a method for testing a device under test. A component of the device under test generates or receives a bus signal, wherein the bus signal comprises a first data signal or a second data signal, and wherein an amplitude of the first data signal is different from an amplitude of the second data signal. A measurement instrument measures an amplitude of the bus signal. Further, it is determined whether the bus signal comprises the first data signal or the second data signal, based on the measured amplitude of the bus signal.

Provided is a test apparatus including an optical test signal generating section that generates an optical test signal; an optical signal supplying section that supplies the optical test signal to a device under test that is a testing target among a plurality of the devices under test; a first optical switch section that selects, from among optical signals output by the plurality of devices under test, the optical signal output by the device under test that is the testing target; and an optical signal receiving section that receives the selected optical signal.

An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.