A chip and a chip testing method are provided. The chip includes a sending terminal circuit and a test circuit. The sending terminal circuit includes a signal sending unit and a first signal bump. The first signal bump is coupled to the signal sending unit. The test circuit is coupled to a circuit node between the signal sending unit and the first signal bump. The test circuit includes a first resistor, a unit gain buffer, and an analog-to-digital converter. A first terminal of the first resistor is coupled to the circuit node. A first input terminal of the unit gain buffer is coupled to a second terminal of the first resistor. A second input terminal of the unit gain buffer is coupled to an output terminal of the unit gain buffer. An input terminal of the analog-to-digital converter is coupled to the output terminal of the unit gain buffer.

A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

An electronic device includes a driver that is connected with a pin, receives an input signal, and outputs an output signal to the pin in response to the input signal, a core circuit that transfers the input signal to the driver, and a monitor circuit that receives the input and output signals and detects a stuck voltage state of the output signal based on the input and output signals. The monitor circuit includes a first detection circuit that detects the stuck voltage state when the input and output signals are logically incorrect, a second detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a low level, and a third detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a high level.

An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.

A multi-channel device with a single diagnosis status pin may be configured to detect if one or more channels has a fault. The multi-channel device, which may operate within a system, can communicate which channel, of a plurality of channels, has the fault using only a single diagnosis status pin and no additional diagnosis control pins. The multi-channel device may output a fault signal on the diagnosis status pin and in response to an interrogation input signal on the same channel as a fault channel indicate to the system which channel is the fault channel.

A system and methods for adaptive bi-direction audio wiring, in which a circuit may be attached via a headset port using RJ9 pin configurations in a phone handset, and dynamically test many different phone handset configurations for optimal audio pathing and processing for speaker and microphone audio generation with minimal noise, static, or power fluctuation.

A semiconductor device includes chips, wherein a first chip: an internal circuit; first selectors to output signals from one of first outputs; second selectors to output signals from one of second outputs; first output buffer units to relay/interrupt signals output from one of the first outputs; second output buffer units to relay/interrupt signals output from one of the second outputs; first terminals to output a signal from the respective first output buffer units and belong to a first group in which the first terminals are placed at positions distant by first distances; and second terminals to output a signal from the respective second output buffer units and belong to a second group in which the second terminals are placed at positions distant by second distances and each of the second terminals is placed at a position distant from an adjacent first terminal of the first terminals by third distances.

The present disclosure provides a method of testing a single device under test (DUT) through multiple cores in parallel, which includes steps as follows. The test quantity of the DUT is calculated; the test quantity of the DUT is evenly allocated to to a plurality of test cores, so as to control a period of testing the DUT through the test cores in parallel.

The semiconductor device includes a first drive control signal generator suitable for generating a first drive control signal from a test input signal, a first output driver suitable for being controlled according to the first drive control signal, a second drive control signal generator suitable for generating a second drive control signal from the first drive control signal, and a second output driver suitable for being controlled according to the second drive control signal.

An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages.