A test system for performing loopback tests is described. The test system includes a processing circuitry and loopback circuitry. The processing circuitry (e.g., module) includes a signal source, an artificial intelligence module, an output port, and an input port, wherein the output port is connected to the input port by the loopback circuitry. The signal source is configured to generate an output signal. The processing module is configured to output the output signal via the output port. The loopback circuitry is configured to at least one of transmit the output signal to the input port directly and transmit the output signal to the input port via at least one further electronic component, thereby obtaining at least one input signal. The input port is configured to receive the at least one input signal. The input port further is configured to forward the at least one input signal to the artificial intelligence module. The artificial intelligence module is configured to automatically perform a loopback test of at least one of the signal source and the further electronic component based on the at least one input signal. Further, an electronic device and a loopback testing method is described.

Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.

Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.

A method for scan chain testing a multi-chip module including a plurality of integrated circuit dice, some of the integrated circuit dice being of a first type and some of the integrated circuit dice being of a second type, includes separately applying a first boundary scan test stream to each die of the first type, and a second boundary scan test stream to each die of the second type. Testing apparatus includes a test interface that couples to each respective test access port, and a controller configured to separately apply the first boundary scan test stream to each die of the first type, and the second boundary scan test stream to each die of the second type. A multi-chip module includes a plurality of integrated circuit dice, each having a boundary scan register chain with a test access port, and a test access port for the module as a whole.

A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

A test assembly for testing an antenna-in-package (AiP) device includes a socket over a circuit board, where the socket includes an opening for receiving the AiP device; a plunger configured to move along sidewalls of the opening, where during testing of the AiP device, the plunger is configured to cause the AiP device to be pressed towards the circuit board such that the AiP device is operatively coupled to the circuit board via input/output connections of the AiP device and of the circuit board; and a loadboard disposed within the socket and between the plunger and the AiP device, where the loadboard includes a coupling structure configured to be electromagnetically coupled to a transmit antenna and to a receive antenna of the AiP device, so that testing signals transmitted by the transmit antenna are conveyed to the receive antenna externally relative to the AiP device through the coupling structure.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a tester system diagnostic method includes forwarding test signals to a loopback component; receiving the test signals from the loopback component; and analyzing the test signals to diagnose whether or not the test system is experiencing problems associated with electrostatic discharges, including analysis of eye scan configuration data corresponding to characteristics of the test signals. In one exemplary implementation, analyzing the eye scan configuration data, including analyzing symmetry of a graphical representation (e.g., eye pattern, eye diagram, etc.) of the eye scan configuration data with respect to a horizontal graphical representation axis.

Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.

A testing device includes a transmitter circuit, a receiver circuit, and a loopback circuit. The transmitter circuit is configured to receive a plurality of first test signals. The receiver circuit is configured to receive input data from a plurality of pads in a normal mode. The loopback circuit is coupled to the plurality of pads and input terminals of a sampler circuit, and the loopback circuit is configured to transmit the plurality of first test signals from the transmitter circuit to the input terminals of the sampler circuit, in order to generate test data for subsequent analysis.