An electronic chip includes an analog input connection pad and an analog output connection pad. A switch is coupled between the analog input connection pad and the analog output connection pad. In one embodiment, the chip operates in a self-test mode and in an active mode. The switch is closed only in the self-test mode.

Embodiments of a method and a device are disclosed. In an embodiment, a method for performing physical layer operations at a network node in a communications network is disclosed. In an embodiment, the method involves identifying a fault status at the network node, embedding an indication of the fault status into a bit stream at the physical layer of the network node, and transmitting the bit stream from the network node. In an embodiment, embedding an indication of the fault status into a bit stream at the physical layer includes embedding an operations, administration, and management (OAM) word into the bit stream to communicate the indication of the fault status.

A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

An embodiment is an automated test equipment (ATE) for testing a device under test (DUT) which is connected to the ATE via a load board. The ATE comprises a stimulus module, a measurement module, a loopback, a first switch, a second switch, and a load board interface. The load board interface comprises a first radio frequency port and a second radio frequency port. The first and second radio frequency ports are configured to be coupled to the respective ports of the load board. The first switch is configured to couple the first radio frequency port to the stimulus module in a first switching state of the first switch and the second switch is configured to couple the second radio frequency port to the measurement module in a first switching state of the second switch. Further, the first switch is configured to couple the first radio frequency port to a first end of the loopback in a second switching state of the first switch and the second switch is configured to couple the second radio frequency port to a second end of the loopback in a second switching state of the second switch. When the first and second switches are in their respective second switching state, a loopback signal path is formed between the first and second radio frequency ports.

An embodiment is an automated test equipment (ATE) for testing a device under test (DUT) which is connected to the ATE via a load board. The ATE comprises a stimulus module, a measurement module, a loopback, a first switch, a second switch, and a load board interface. The load board interface comprises a first radio frequency port and a second radio frequency port. The first and second radio frequency ports are configured to be coupled to the respective ports of the load board. The first switch is configured to couple the first radio frequency port to the stimulus module in a first switching state of the first switch and the second switch is configured to couple the second radio frequency port to the measurement module in a first switching state of the second switch. Further, the first switch is configured to couple the first radio frequency port to a first end of the loopback in a second switching state of the first switch and the second switch is configured to couple the second radio frequency port to a second end of the loopback in a second switching state of the second switch. When the first and second switches are in their respective second switching state, a loopback signal path is formed between the first and second radio frequency ports.

Embodiments according to the disclosure comprise an automated test equipment component, ATE component, e.g., a handler component, e.g., a handler arm, comprising a first antenna adapted to establish a wireless, e.g., near field, coupling with a device under test (DUT), e.g., comprising an antenna, e.g., comprising an antenna array, when the DUT is arranged on a loadboard, e.g., a DUT loadboard. Furthermore, the ATE component comprises a second antenna for establishing a wireless, e.g., near field, coupling with a characterizing device, e.g., a golden device, e.g., comprising an antenna, e.g., comprising an antenna array, when the characterizing device is arranged, e.g., placed, on the loadboard, wherein the DUT and the characterizing device are, for example, placed at different positions on the DUT loadboard. Moreover, the first antenna is electrically coupled, e.g., connected with a rigid electrical connection, with the second antenna, to allow for a forwarding of a signal, e.g., of a plurality of signals, provided, e.g., transmitted, by the DUT to the characterizing device, e.g., reference device, and/or vice versa, e.g., to allow for a forwarding of a signal, e.g., of a plurality of signals, provided, e.g., transmitted, by the characterizing device to the DUT. Optionally, a relative position of the second antenna with respect to the first antenna may be fixed, or for example, a relative position of the second antenna with respect to the first antenna may be variable.

A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

Methods, systems, and devices for testing a die using a segmented digital die ring are described. A segmented digital die ring may include multiple signal line segments, each coupled with a test segment circuit, and a control circuit. A test segment circuit may generate a digital feedback signal that indicates a condition of a respective signal line segment. The control circuit may generate a single output signal, indicative of the condition of the signal line segments. By utilizing digital testing circuitry and a single digital output signal, a layout area of the segmented digital die ring be minimized and a power consumption associated with the testing operation may be reduced.

One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.