An electric meter that is configured to regenerate meter state data after a power loss includes a memory with at least one volatile and non-volatile memory device and a processor connected to the memory. The processor is configured to retrieve a backup copy of meter state data and a plurality of meter input data samples that were generated after the backup copy of the meter state data and prior to the power loss from a non-volatile memory device. The processor is configured to regenerate meter state data by updating the backup copy of meter state data with the plurality of meter input data samples to regenerate the meter state data at the time of a final meter input data sample prior to the power loss.

Methods and systems are described to efficiently identify the potential for failures in integrated circuits (ICs) caused by glitches. In an IC based on synchronous operation, the operation of the multiplicity of inputs, storage elements and observed outputs in said IC are synchronized to one or more clocks that determine the specific times at which inputs change, outputs are observed, and stored values are updated. Almost all ICs are based on synchronous operation. When input values to a logic circuit in an IC change, the effects of said changes propagate through paths in said logic circuit in a delayed manner such that each of said paths may have a different delay. Said different delays can cause a wire in a logic circuit to have transient values (termed glitch) before settling to a final value consistent with the input values being applied to said logic circuit. An IC is likely to function erroneously, referred to as having a glitch failure, when a glitch value is observed at an output or captured by a storage element. Glitch failures are difficult and expensive to diagnose in a manufactured IC. To raise the productivity of IC development, it is imperative that any potential glitch failure in an IC be detected prior to manufacture. Said detection is hard because a typical IC has a very large number of logic circuits to analyze for glitch failure. To be practical, said analysis must have high performance and high accuracy. Said high performance requiring that said analysis should complete in acceptable run time even for the largest ICs. Said high accuracy requires that said analysis should identify all potential for glitch failure (100% recall), and minimize the number of logic circuits erroneously reported as having glitch failure potential (high precision). Whereas the glitch phenomenon, the potential for glitch failure and methods for detecting glitch failures in pre-manufacture IC models are well known, achievement of high performance with high accuracy has not yet been addressed in prior art. Whereas conventional methods for glitch checking are inefficient and insufficiently accurate, the methods and systems described in the present invention achieve new levels of performance, scalability and accuracy in said detection of glitch failures in an IC. Said methods and systems are based on a novel dissection of glitch-checking requirements into a multiplicity of individual steps, which said steps executed in a systematic sequence deliver high performance and accuracy.

A non-transitory computer-readable recording medium stores a test pattern generation program for causing a computer to execute processing including: detecting, based on design information of a semiconductor integrated circuit, a plurality of clock domains each of which operates according to any one of a plurality of clock signals; changing application order of the plurality of clock signals when a test pattern that includes the application order and a first input value to a first object circuit is generated, based on which of the plurality of clock domains a first holding circuit that sends the first input value or a first response value from the first object circuit to the first circuit region and a second holding circuit that receives the first response value from the first circuit region, belong to; and outputting information regarding the test pattern.

A scan controller provides a translation between a two terminal external interface and a four signal line internal scan interface to a digital core of the integrated circuit. The two terminal external interface has an input terminal and an input/output terminal. The input terminal receives a clock signal and the input/output terminal serially receives a scan enable signal and a scan in data bit. A state machine controls the scan controller. The scan in data bit, the scan enable signal, and a scan clock signal are supplied in parallel to the internal scan interface. The digital logic provides a scan out data bit and the scan controller supplies the scan out data bit over the input/output terminal in synchronism with the clock signal.

A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

An example process for aligning channels in automatic test equipment (ATE) includes programming a first delay associated with receiving first data over a channel so that timing of the channel is aligned to timings of other channels in the ATE; programming a second delay associated with a driver driving second data over the channel based on receipt of an edge of the second data so that timing of the second data is aligned to the timing of the channel; and programming a third delay associated with a signal to enable the driver to drive the second data over the channel, with the third delay being programmed to align timing of the signal to the timing of the channel, and with the third delay being based on an edge that corresponds to an edge of the signal created by controlling operation of the driver.

The present invention relates to a method for calibrating a channel delay skew of automatic test equipment (ATE), the method comprising: providing multiple calibration reference devices, wherein the calibration reference devices have a second plurality of delay paths each having a predetermined path delay value and coupling a pair of pins of one of the calibration reference devices together, wherein each pin is coupled to at most one delay path; coupling each of the calibration reference devices with the ATE, respectively, wherein the test probe of each of the first plurality of test channels is coupled with a pin of one of the calibration reference devices; testing the calibration reference devices to obtain multiple delay measurements from one or more transmitting channels of the first plurality of test channels to one or more receiving channels of the first plurality of test channels using the ATE; and calculating based on the delay measurements.

There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.

Devices and techniques are disclosed herein for debugging a device implemented on a die using non-test pins. An instruction to enable a debugging mode of operation is received with a memory device implemented at least in part on a die. In response to receiving the instruction, functionality of a first non-test pin of the die is modified to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die. A debugging clock signal is established using a signal received at a second non-test pin of the die. Information including the debugging data is exchanged between the die and the debugging component using the first and second non-test pins of the die.