This application is directed to methods and devices of detecting and correcting a fault in an integrated circuit. A latching circuit outputs a first voltage level at an output, and a function control signal is generated to hold the first voltage level outputted by the latching circuit. A single event upset originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level. When the single event upset is detected, the latching circuit is controlled via a clear signal to reset its output to the first voltage level. A glitch is thereby formed on the first voltage level at the output of the latching circuit. The glitch is suppressed at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.

A semiconductor device includes: a first line; a second line that is not connected to the first line and is provided to transfer a signal having a level same as a level of a signal transferred through the first line; and another line different from the first line and the second line. In a line layer, a distance between the first line and the second line is longer than a distance between the first line and the other line, and is longer than a distance between the second line and the other line.

A method tests a plurality of devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices. The test data in the test chains of the devices is shifted forward by one position. The shifting includes writing test data in the last position of a test chain to a first position in the test chain. The comparing and the shifting are repeated until the test data in the last position of each test chain when the testing is started is shifted back into the last position of the respective test chain. The plurality of devices may have a same structure and a same functionality.

The memory error determination device includes a processor configured to: detect a memory element in which an error has occurred in each of a plurality of layers included in a memory being three-dimensionally stacked, specify a position of each memory element in which the error has occurred in each of the plurality of layers, and determine that, when the position of each memory element in which the error has occurred is linearly aligned across a predetermined number of layers among the plurality of layers, the predetermined number being two or more, an error that has occurred in the memory is a soft error due to radiation incident on the memory.

In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.

Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.

Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.

This application is directed to methods and devices of detecting and correcting a fault in an integrated circuit. A latching circuit outputs a first voltage level at an output, and a function control signal is generated to hold the first voltage level outputted by the latching circuit. A single event upset originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level. When the single event upset is detected, the latching circuit is controlled via a clear signal to reset its output to the first voltage level. A glitch is thereby formed on the first voltage level at the output of the latching circuit. The glitch is suppressed at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.

Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.

A nuclear reaction detection device includes an FPGA (Field Programmable Gate Array) 100 which is arranged in an environment in which particle radiation is incident, and includes a user circuit 101 configured to output a value different from that in a normal state, if an SEU (Single Event Upset) occurs in a semiconductor element included in the FPGA, and an SEF detection unit 210 which detects that an abnormal operation (SEF) has occurred in the user circuit based on the output value from the user circuit 101 of the FPGA 100.