An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

A method tests at least three devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices, and shifting test data in the test chains of each of the devices and storing a result of the comparison in a first position of the test chains of each of the devices. The comparing and the shifting and storing are repeated until all the stored test data has been compared. The at least three devices may have a same functionality and a same structure.

A method tests a plurality of devices, each device including a test chain having a plurality of positions storing test data. The testing includes comparing test data in a last position of the test chain of each of the devices. The test data in the test chains of the devices is shifted forward by one position. The shifting includes writing test data in the last position of a test chain to a first position in the test chain. The comparing and the shifting are repeated until the test data in the last position of each test chain when the testing is started is shifted back into the last position of the respective test chain. The plurality of devices may have a same structure and a same functionality.

The memory error determination device includes a processor configured to: detect a memory element in which an error has occurred in each of a plurality of layers included in a memory being three-dimensionally stacked, specify a position of each memory element in which the error has occurred in each of the plurality of layers, and determine that, when the position of each memory element in which the error has occurred is linearly aligned across a predetermined number of layers among the plurality of layers, the predetermined number being two or more, an error that has occurred in the memory is a soft error due to radiation incident on the memory.

An example apparatus includes an input buffer coupled to an input terminal, wherein the input buffer is configured to provide an input signal based on a voltage received at the input terminal, a test terminal configured to receive a probe signal, and a power supply terminal configured to receive an external supply voltage. The example apparatus further includes a test logic circuit configured to, in response to the probe signal indicating a test and an external supply voltage detection signal having a value indicating detection of the external supply voltage, initiate a probe contact detection test. During the initiate a probe contact detection test, the test logic circuit is configured to receive the input signal and to provide an output signal having a value based on the input signal.

An example apparatus includes an input buffer coupled to an input terminal, wherein the input buffer is configured to provide an input signal based on a voltage received at the input terminal, a test terminal configured to receive a probe signal, and a power supply terminal configured to receive an external supply voltage. The example apparatus further includes a test logic circuit configured to, in response to the probe signal indicating a test and an external supply voltage detection signal having a value indicating detection of the external supply voltage, initiate a probe contact detection test. During the initiate a probe contact detection test, the test logic circuit is configured to receive the input signal and to provide an output signal having a value based on the input signal.

This application is directed to methods and devices of detecting and correcting a fault in an integrated circuit. A latching circuit outputs a first voltage level at an output, and a function control signal is generated to hold the first voltage level outputted by the latching circuit. A single event upset originates within the latching circuit and causes the first voltage level at the output of the latching circuit to transition to a second voltage level. When the single event upset is detected, the latching circuit is controlled via a clear signal to reset its output to the first voltage level. A glitch is thereby formed on the first voltage level at the output of the latching circuit. The glitch is suppressed at the output of the latching circuit to generate the function control signal holding the first voltage level without the glitch.

Digital testing is performed on an integrated circuit while radiation upsets are induced at locations of the integrated circuit. For each digital test, a determination is made as to whether there is a variation in the output of the digital test from an expected output of the digital test. If there is variation, a time of the variation is indicated. In one example, a location of a defect in the digital circuit can be determined from the times of the variations. In other embodiments, a mapping of the digital circuit can be made from the times.

A method is provided for analyzing failure rates due to soft/hard errors in the design of a digital electronic device. The method includes creating an error injection point by introducing a fault into a code path having a plurality of levels; determining an error detection point at which the introduced fault becomes detectable; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list; determining the intersection between the first and second logic cone lists; and conducting a failure rate analysis on the intersection between the first and second logic cone lists.

A method for generating redundant configuration in FPGA devices includes: analysing the configuration pertaining to a given design to be configured, or already configured, in the FPGA device, in order to identify programmed and empty configuration memory portions, configuring the FPGA device for implementing said design, measuring the power consumption of the configured FPGA device, copying the configuration from at least some subsets of the programmed portion to subsets of the empty portion, (a) verifying the configuration read back from said subsets of the empty portion with the configuration data read from said subsets of the programmed portion, (b) verifying whether the functionality of the design after the copy is still correct, (c) measuring the power consumption of the FPGA device, and verifying whether the power consumption of the FPGA device after the copy is acceptable according to pre-defined criteria, if the verification steps (a), (b) and (c) are all successful the redundant configuration is correctly generated, and if the verification steps (a), (b) and (c) are not all successful the method restarts from the beginning choosing other subsets of the empty portion of the FPGA device for hosting the configuration data from said subsets of the programmed portion.