Neutron soft error rate derivation is calculated from data at the low energy neutron radiation. An outline value of an SEU cross-section function corresponding to a given neutron energy value is outputted. This outline value and the low energy neutron spectrum data are used to calculate an error count basic value of errors to occur over time. An error count actual measurement value over time is calculated from an error count during radiation of low energy neutrons and low energy neutron radiation time. The error count basic value and the error count actual measurement are used to calculate a proportionality coefficient of the SEU cross-section function. While holding a natural neutron spectrum, an error rate calculator outputs a neutron flux corresponding to a neutron energy value. The neutron soft error rate is calculated by an integration operation of multiplying the SEU cross-section function with the natural neuron spectrum.

Methods and apparatus are described for detecting both single event latch-up (SEL) and electrical overvoltage stress (EOS) using a single, reconfigurable detection circuit. One example circuit capable of detecting a latch-up state and an overvoltage condition generally includes an impedance element coupled to a power supply node; a voltage divider coupled to the power supply node; a multiplexer having a first input coupled to a tap of the voltage divider, a second input coupled to a first portion of the impedance element, and a third input coupled to a second portion of the impedance element; a reference generator; and an analog-to-digital converter (ADC) having a first input coupled to an output of the multiplexer and a second input coupled to an output of the reference generator.

A semiconductor test device includes an actuator holding a radiation source and adjusting a distance between the radiation source and a sample, and a controller controlling an operation of the actuator and calculating a soft error rate (SER) of the sample based on the distance between the radiation source and the sample. The controller calculates a first distance between the radiation source and the sample at which the SER of the sample becomes zero, and calculates a metal-to-dielectric ratio of the sample based on the first distance.

Disclosed are exemplary embodiments of transient scanning data visualization methods and systems. Also disclosed are exemplary embodiments of embedded transient scanning systems and methods.

A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.

An apparatus including a chamber is provided herein. The chamber includes: a radiation source; a load board slot configured for: (i) holding a load board; and (ii) connecting the load board to an automatic testing equipment; The chamber further includes at least one movable device for positioning the load board slot relative to the radiation source or positioning the radiation source relative to the load board slot; and a controller for receiving instructions and controlling the at least one movable device according to the received instructions. Said chamber, including the automatic testing equipment, is configured for constructing and operating soft errors testing by positioning the load board slot relative to the radiation source or by positioning the radiation source relative to the load board slot.

A method is provided for analyzing failure rates due to soft/hard errors in the design of a digital electronic device. The method includes creating an error injection point by introducing a fault into a code path having a plurality of levels; determining an error detection point at which the introduced fault becomes detectable; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error detection point, thereby generating a first logic cone list; creating a list of all of the logic cells forming the cone of logic that forms the data input to the error injection point, thereby generating a second logic cone list; determining the intersection between the first and second logic cone lists; and conducting a failure rate analysis on the intersection between the first and second logic cone lists.

Disclosed herein is a test circuit for a 3D semiconductor device for detecting soft errors and a method for testing thereof. The test circuit includes a first Multiple Input Signature Register (MISR) disposed in a first semiconductor chip, the first MISR compressing a first test result signal corresponding to a test pattern, a second MISR disposed in a second semiconductor chip stacked on or under the first semiconductor chip, the second MISR compressing a second test result signal corresponding to the test pattern, and a first error detector to detect a soft error by comparing a first output signal output from the first MISR with a second output signal output from the second MISR.

Described herein is a method implemented by circuitry for providing fault tolerance in a combinational circuit. The circuitry identifies sensitive gates of the circuit that require protection from at least one of a first type of fault and a second type of fault. Further, circuitry computes for each first type of transistor included in the sensitive gate, a first failure probability, and for each second type of transistor included in the sensitive gate, a second failure probability. The circuitry calculates a first parameter corresponding to a number of the first type of transistors for which the computed first failure probabilities exceed a first predetermined threshold and a second parameter corresponding to a number of second type of transistors for which the computed second failure probabilities exceed a second predetermined threshold to determine a protection type based on an area overhead constraint.

Described is a chip comprising: a substrate; a logic unit forming an active circuit on the substrate; and a cosmic ray detector embedded in the substrate, the cosmic ray detector to detect a cosmic ray and to generate a signal indicating detection of the cosmic ray, the signal for reducing error in the logic unit.