A system comprises a plurality of regions, wherein ones of the plurality of regions are partitioned from others of the plurality of regions and at least one of the plurality of regions is a region under test. The system comprises at least one noise generator configured to generate noise in at least the region under test, and at least one noise monitor configured to monitor one or more effects of the noise generated in the region under test. The system comprises a test controller configured to: cause the at least one noise generator to generate the noise in at least the region under test; receive information from the at least one noise monitor indicative of the one or more effects of the noise generated in the region under test; and determine one or more conditions based on at least a portion of the received information.

A simulation method and system of verifying an operation of a semiconductor memory device of a memory module at a design level. The simulation method includes setting a configuration and an arrangement of a registered clock driver (RCD) and a configuration and an arrangement of first semiconductor memory devices to fourth semiconductor memory devices, on a printed circuit board (PCB) through a graphic user interface (GUI). When a RCD test execution command is applied through the GUI, executing a test program to apply control signals to control signal terminals of the PCB based on a command truth table, to compare the applied control signals and control signals output through first driver output terminals of the RCD, and to create an RCD test result. When the RCD operates normally, performing a test on the memory module.

A storage unit is used for storing a plurality of interface units. A disposition system then automatically manages interface units. A carrier is provided for accommodating an interface unit. The interface unit is configured for testing semiconductor elements in corresponding test devices. The storage unit is designed for storing a plurality of interface units, the storage unit having a plurality of compartments, each for accommodating one carrier, and each such carrier being designed to accommodate one interface unit. The storage unit comprises at least one alignment element for positionally accurate coupling of a handling device.

One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

The present application relates to a circuit simulation test method and apparatus, a device, and a medium. The method includes: creating a parametric data model, wherein the parametric data model is configured to generate preset write data based on a preset parameter; creating a test platform, wherein the test platform is configured to generate a test result based on the preset write data; creating an eye diagram generation module, wherein the eye diagram generation module is configured to generate a data eye diagram based on the test result; and conducting a simulation test, inputting the preset write data to the test platform and obtaining the test result, and generating the data eye diagram by using the eye diagram generation module.

A failure pattern obtaining method and apparatus are provided. The method includes that: a chip test result picture for a wafer is obtained, the chip test result picture being marked with a plurality of failure test points; a vector for every two points among all failure test points is calculated; a plurality of failure test points having a same vector are designated as a same group; a plurality of pending failure patterns are separated from each of groups; a failure pattern is obtained based on the plurality of the pending failure patterns.

A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

The present disclosure describes exemplary methods and systems that are applicable for hardware authentication, counterfeit detection, and in-field tamper detection in both printed circuit board and/or integrated circuit levels by utilizing random variations in boundary-scan path delay and/or current in the industry-standard JTAG-based design-for-test structure to generate unique device identifiers.

A method for real-time firmware configuration and a debugging apparatus are provided. When a demand for updating or debugging a target processor raises, in the method, a computer system generates a firmware debugging request that is attached with a firmware data with a specific debugging function. The computer system then loads the firmware data to a programmable logic unit of the debugging apparatus. After the real-time firmware configuration is completed, the computer system issues a debugging command to the programmable logic unit. The programmable logic unit obtains at least one debugging action after resolving the debugging command. The at least one debugging action is performed in the target processor when the target processor receives the at least one debugging action. A debugging result is returned after the at least one debugging action is completed.

The present disclosure describes a method for analyzing signal waveforms produced by integrated circuits. The method includes determining characteristic points of a control signal, and each characteristic point includes a corresponding time value and represents an edge change of the control signal. The method also includes determining sets of data sampling points. Each set of data sampling points is located between adjacent characteristic points of the characteristic points. The method further includes obtaining data values of a signal waveform, and a data value of the signal waveform is obtained at a data sampling point of the sets of data sampling points. The method further includes obtaining data values of a reference waveform, and a data value of the reference waveform is obtained at the data sampling point and determining a difference between the data value of the signal waveform and the data value of the reference waveform.