System analysis by receiving a model of a complex system design. The model includes at least one layer. The analysis includes performing a plurality of simulations of the performance of the layer. The number of simulations is determined according to a number of system components associated with the layer. The analysis further includes determining a worst-case result for a set of simulations from the plurality of simulations and assigning the worst-case result to an overall system simulation.

Embodiments relate to a system, program product, and method for integrating compiler-based testing in post-silicon validation. The method includes generating a test program through a device-under-test (DUT). The method also includes generating a plurality of memory intervals and injecting the plurality of memory intervals into the test program. The method further includes injecting a plurality of compiled test snippets into the test program and executing one or more post-silicon validation tests for the DUT with the test program.

A high-frequency coaxial attenuator includes a first coaxial cable portion that includes a first center conductor having a first length, and a first insulator of the first length formed around the first center conductor, wherein the first center conductor and the first insulator form a first diameter. A second coaxial cable portion is separated from the first coaxial cable portion by a gap. The second coaxial cable portion includes a second center conductor having a second length, and a second insulator of the second length formed around the second center conductor. A semiconductor material is deposited in the gap between the first coaxial cable portion and the second coaxial cable portion. The semiconductor material may be configured to provide an impedance of 500Ω and provides 20 dB of attenuation, and a 10:1 voltage divider based on a 50Ω input impedance of test equipment.

A test and measurement system includes a machine learning system, a test and measurement device including a port configured to connect the test and measurement device to a device under test (DUT), and one or more processors, configured to execute code that causes the one or more processors to: acquire a waveform from the device under test (DUT),transform the waveform into a composite waveform image, and send the composite waveform image to the machine learning system to obtain a bit error ratio (BER) value for the DUT. A method of determining a bit error ratio for a device under test (DUT), includes acquiring one or more waveforms from the DUT, transforming the one or more waveforms into a composite waveform image, and sending the composite waveform image to a machine learning system to obtain a bit error ratio (BER) value for the DUT.

A test and measurement system includes a test and measurement device configured to receive a signal from a device under test, and one or more processors configured to execute code that causes the one or more processors to generate a waveform from the signal, apply an equalizer to the waveform, receive an input identifying one or more measurements to be made on the waveform, select a number of unit intervals (UIs) for a known data pattern, scan the waveform for the known data patterns having a length of the number of UIs, identify the known data patterns as short pattern waveforms, apply a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and provide the values of the one or more measurements for the waveform. A method includes receiving a signal from a device under test, generating a waveform from the signal, applying an equalizer to the waveform, receiving an input identifying one or more measurements to be made on the waveform, selecting a number of unit intervals (UIs), scanning the waveform to identify short pattern waveforms having a length equal to the number of UIs, applying a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and providing the values of the one or more measurements for the waveform from the machine learning system.

Arrangements and techniques for testing mobile devices within a test module. The test modules are portable and may be stacked to provide a modular testing system. A pulley system may be used to move an actuator arm horizontally in the X and Y directions. The actuator arm may be moved vertically in the Z direction such that a tip may engage a touchscreen of a mobile device being tested or a user interface element of the mobile device.

A device may determine an analog gain for an aggregated analog signal. The aggregated analog signal may be associated with a calibration test to be used to determine a set of calibration parameters for a load test of a base station. The device may determine the set of calibration parameters for the load test based on an outcome of performing a calibration test. The set of calibration parameters may result in a set of digital gains approximately centered in a digital dynamic gain range. The device may perform the load test after determining the analog gain for the analog signal and based on the set of calibration parameters for the load test.

An integrated circuit test apparatus includes: a first test unit configured to output a current for a built-in self test (BIST) progress state for each internal circuit of an integrated circuit in a BIST test mode and to determine whether each internal circuit operates normally in a wake-up mode of the integrated circuit; and a first determination module configured to determine whether each internal circuit is in a stuck state based on a change detected by the first test unit.

A test system may be used for obtaining accurate remote sense voltage and/or current values. A measurement instrument may provide a regulated stimulus signal to a device under test (DUT) and measure a DUT signal developed at least partially in response to the stimulus signal. A test circuit may superimpose a test signal over the stimulus signal to cause the DUT signal to be developed further in response to the test signal. The DUT signal may be used to derive a resistance of the path that couples the measurement instrument to the DUT. The measurement instrument may include a source measure unit, the stimulus signal may be a regulated voltage, and the DUT signal may be a sense voltage. The harmonics of the DUT signal may be analyzed to determine a correlation between an amplitude of a measured fundamental frequency of the DUT signal and the resistance of the path.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.