Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a ring oscillator and a register for storage of a value indicative of an interval of time. Each instance of the measuring circuit is configured to measure passage of the interval of time based on a first clock signal, count oscillations of an output signal of the ring oscillator during the interval of time, and output a value indicating a number of oscillations counted during the interval of time.

A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.

An automated test equipment comprises a tester control configured to broadcast and/or specific upload to matching module input data and/or device-specific data including keys and/or credentials and/or IDs and/or configuration information. The automated test equipment further comprises a channel processing unit configured to transform input data using device specific data in order to obtain device-under-test adapted data for testing the device under test. The channel processing unit further configured to process the DUT data using device specific data in order to evaluate the DUT data. A method and a computer program for testing one or more devices under test in an automated test equipment are also disclosed.

The invention describes an integrated circuit, comprising a functional circuit structure which is configured to provide a functionality; and a test structure configured to set a signal, which is coupled to the functional circuit structure, to a test value in response to a magnetic field impulse, to control a test of the integrated circuit. The invention also describes an apparatus and a method for testing an integrated circuit and a computer program implementing the method. This invention provides a time-effective and cost-effective concept of component testing using magnetic interaction.

The invention describes an integrated circuit, comprising a functional circuit structure which is configured to provide a functionality; and a test structure configured to set a signal, which is coupled to the functional circuit structure, to a test value in response to a magnetic field impulse, to control a test of the integrated circuit. The invention also describes an apparatus and a method for testing an integrated circuit and a computer program implementing the method. This invention provides a time-effective and cost-effective concept of component testing using magnetic interaction.

A method includes receiving tester configuration data, test pattern data, and tester operation data; configuring a circuit for performing a designated test evaluation; generating a stimulus waveform; converting the stimulus waveform to an analog stimulus signal; transferring the analog stimulus signal to a first terminal of a MTJ DUT at reception of a trigger timing signal; generating time traces based on the trigger timing signal; generating a response signal at a second terminal of the MTJ DUT and across a termination resistor as the analog stimulus signal is transferred through the MTJ DUT; converting the response signal to a digitized response signal indicating its voltage amplitude; and performing the designated test evaluation and analysis function in the configurable circuit based on voltage amplitudes and time values of the stimulus waveform, the digitized response signal, and the timing traces.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

A storage unit is used for storing a plurality of interface units. A disposition system then automatically manages interface units. A carrier is provided for accommodating an interface unit. The interface unit is configured for testing semiconductor elements in corresponding test devices. The storage unit is designed for storing a plurality of interface units, the storage unit having a plurality of compartments, each for accommodating one carrier, and each such carrier being designed to accommodate one interface unit. The storage unit comprises at least one alignment element for positionally accurate coupling of a handling device.