The present application relates to a circuit simulation test method and apparatus, a device, and a medium. The method includes: creating a parametric data model, wherein the parametric data model is configured to generate preset write data based on a preset parameter; creating a test platform, wherein the test platform is configured to generate a test result based on the preset write data; creating an eye diagram generation module, wherein the eye diagram generation module is configured to generate a data eye diagram based on the test result; and conducting a simulation test, inputting the preset write data to the test platform and obtaining the test result, and generating the data eye diagram by using the eye diagram generation module.

A tool with three pins arranged in a row that three pinholes arranged in a row such as those found on a motor controller could easily connect to and disconnect from, that, when connected to a motor controller, identifies which of the three wires is positively charged, and whether the voltage difference is above 9 volts. Should one of the outer two wires be positively charged, and consequently not the middle one, or should the voltage difference be greater than 9 volts, then the motor controller would be faultily wired, consequently breaking any receiver that the motor controller connects to.

A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

A wafer test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.

The invention is an assembly for checking the functionality of a measuring object, that is a DUT, in a medical implant or at least one part of the medical implant. The assembly comprises a test signal generator, a test module that is connected to the test signal generator. The assembly has a first receiving structure with at least one contact electrode, into which an adapter rigidly connects to the DUT in a releasable manner which is inserted to form least one electrical contact. A control and analysis unit is connected to the test signal generator and to the test module in a wired or wireless manner.

Methods, systems and techniques are provided to authenticate a device under test (DUT)/system under test (SUT) comprising an electronic component(s). A profile is defined by injecting a signal to elicit an output that is responsive a physical characteristic of the type of DUT/SUT. In respective embodiments the injected signal is defined to elicit an output for time-domain or frequency-domain evaluation. An injected signal may comprise combinations of (non-destructive/non-activating) signals applied to multiple access points for measurement at arbitrary access points of the DUT/SUT. In an embodiment, measurements of multiple DUT/SUTs of a same type are used to define a common profile. In an embodiment, the profile is built using machine learning to define a classifier. In other embodiments, statistical profiles are defined. During use, output is generated for a target DUT/SUT for evaluation relative to the profile. Counterfeit/alternate designs, altered designs, and implants are detectable.

A debug system includes a chip to be tested and a debug controller. The chip to be tested includes a circuit to be tested, a debug access circuit and a debug protection circuit. When a protection function is not enabled, the debug protection circuit enables a communication between the debug access circuit and the chip to be tested, the debug controller accesses the data of the chip to be tested via the debug access circuit for debugging the circuit to be tested. When the protection function is enabled, the debug protection circuit blocks the communication between the debug access circuit and the chip to be tested, the debug controller transmits a message to the debug protection circuit via the debug access circuit, and the debug protection circuit determines whether to disable the protection function according to the message.

There is provided an attenuation amount setting unit that sets, in a case where signals are simultaneously output from all output ports of a plurality of interface units at the same signal level, one of the plurality of interface units as the reference interface unit, and adds a difference between an attenuation amount of a second attenuator stored in a storage unit of the reference interface unit and an attenuation amount of another second attenuator stored in another storage unit of the other interface unit to an attenuation amount of each of a plurality of third attenuators of the other interface unit to correct the attenuation amount.

Arrangements and techniques for testing mobile devices within a test module. The test modules are portable and may be stacked to provide a modular testing system. A pulley system may be used to move an actuator arm horizontally in the X and Y directions. The actuator arm may be moved vertically in the Z direction such that a tip may engage a touchscreen of a mobile device being tested or a user interface element of the mobile device.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.