Systems and methods for detecting the presence and/or location of defects (e.g., incomplete solders, broken cables, misconnections, defective sockets, opens, shorts, etc.) along electrical lines are described. The systems and methods described herein may use time-domain reflectometry (TDR), a measurement technique used to determine the characteristics of electrical lines by observing reflected waveforms. TDR may be performed in some embodiments by determining the times when a first event and a second event occur, and by determining the space traveled by a probe signal based on these times. The first event may occur when a first signal transition crosses a first threshold and the second event may occur when a second signal transition crosses a second threshold, where the second signal transition may arise in response to the first signal transition reflecting against a defect along the electrical line.

A method for detecting errors or malfunctions in electrical or electronic components of circuits, wherein each of the circuits is located on a circuit board and wherein a plurality of circuit boards border one another on a circuit board panel, includes populating each of the circuit boards of the circuit board panel with electrical or electronic components corresponding to the circuits; for each of the analog, electrical or electronic components used for the construction of the circuits, placing a corresponding test component in an edge region of the circuit board panel; providing the analog, electrical or electronic test components placed in the edge region of the circuit board panel with test points; and checking for the correct function value and/or the correct poling of the analog, electrical or electronic test components provided with test points and located in the edge region of the circuit board panel.

A method for detecting errors or malfunctions in electrical or electronic components of circuits, wherein each of the circuits is located on a circuit board and wherein a plurality of circuit boards border one another on a circuit board panel, includes populating each of the circuit boards of the circuit board panel with electrical or electronic components corresponding to the circuits; for each of the analog, electrical or electronic components used for the construction of the circuits, placing a corresponding test component in an edge region of the circuit board panel; providing the analog, electrical or electronic test components placed in the edge region of the circuit board panel with test points; and checking for the correct function value and/or the correct poling of the analog, electrical or electronic test components provided with test points and located in the edge region of the circuit board panel.

To facilitate a reliable detection of age-related damage or delamination on components the following is proposed: [i] within the scope of radiofrequency reflectometry, scanning a component by radiofrequency signal irradiation in the micrometer or millimeter wavelength range and by measuring at least one reflection signal, which was reflected at the component, in punctiform, one-dimensional or two-dimensional fashion for the purposes of generating at least one first radiofrequency image representation; [ii] scanning the component in direct time offset fashion with respect to the radiofrequency signal irradiation by a combination of ultrasonic signal irradiation and the radiofrequency signal irradiation in the micrometer or millimeter wavelength range and by measuring at least one further reflection signal, which was reflected at the component; and [iii] comparing the radiofrequency image representations generated based on the reflection signals, wherein determined changes in the radiofrequency image representations indicate damage or delamination on the component.

A control device including a solder joint life predictor includes: a temperature sensor that measures temperature of a solder joint on an electronic circuit board that drives a heater and a motor; a storage that stores a reference acceleration factor that is an acceleration factor based on a test condition of a thermal shock test and a reference condition in an environment in which the electrical appliance is used; a calculator that calculates an actual acceleration factor from a temperature variation range and a maximum reached temperature of the solder joint during one cycle from start to end of driving of the heater or the motor; and a determiner that predicts the life of the solder joint by comparing the integrated value of the acceleration factor ratios with a threshold.

A plurality of test pads are formed on a first substrate or a second substrate. A plurality of first solder joints are reserved on a first surface of the first substrate, and each of the first solder joints is coupled to at least a test pad or to another first solder joint through at least a first trace. A plurality of second solder joints are reserved on a second surface of the second substrate. Each of the second solder joints is coupled to at least a test pad or to another second solder joint through at least a second trace. A plurality of dummy solder balls are formed between the first solder joints and the second solder joints. Probes are coupled to the test pads to measure circuit characteristics between the test pads.

A plurality of test pads are formed on a first substrate or a second substrate. A plurality of first solder joints are reserved on a first surface of the first substrate, and each of the first solder joints is coupled to at least a test pad or to another first solder joint through at least a first trace. A plurality of second solder joints are reserved on a second surface of the second substrate. Each of the second solder joints is coupled to at least a test pad or to another second solder joint through at least a second trace. A plurality of dummy solder balls are formed between the first solder joints and the second solder joints. Probes are coupled to the test pads to measure circuit characteristics between the test pads.

A semiconductor device includes first and second power supply terminals to which a first power supply voltage is supplied, a third power supply terminal to which a second power supply voltage is supplied, a power supply wiring coupled to the first and second power supply terminals, an abnormality detection circuit which diagnoses the first power supply terminal, a first current generation circuit which flows a current from the power supply wiring to the third power supply terminal in a diagnosis, and a second current generation circuit which couples to the power supply wiring at a vicinity of the first power supply terminal and flows a current from the power supply wiring to the third power supply terminal in the diagnosis. And, the abnormality detection circuit compares a voltage of the first current generation circuit with a voltage of the second current generation circuit in the diagnosis.

A semiconductor device includes first and second power supply terminals to which a first power supply voltage is supplied, a third power supply terminal to which a second power supply voltage is supplied, a power supply wiring coupled to the first and second power supply terminals, an abnormality detection circuit which diagnoses the first power supply terminal, a first current generation circuit which flows a current from the power supply wiring to the third power supply terminal in a diagnosis, and a second current generation circuit which couples to the power supply wiring at a vicinity of the first power supply terminal and flows a current from the power supply wiring to the third power supply terminal in the diagnosis. And, the abnormality detection circuit compares a voltage of the first current generation circuit with a voltage of the second current generation circuit in the diagnosis.

Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.