Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.

A ball grid array device includes a monitoring circuit of inactive solder joints and a processor such as a field programmable gate array (FPGA) or other processor capable of determining the open or closed status of the monitoring circuit. The monitoring circuit traverses one or more of the solder joints between components being joined, such as a printed circuit board and an integrated circuit device. In certain embodiments, the inactive solder joints may be located within regions of the ball grid array that are predisposed to failure, such as at the periphery or corners of the printed circuit board, or proximate to regions that experience a broad range of operating temperatures. The failure of a solder joint within the monitoring circuit can be used to schedule maintenance of the ball grid array device prior to failure of an active solder joint.

A ball grid array device includes a monitoring circuit of inactive solder joints and a processor such as a field programmable gate array (FPGA) or other processor capable of determining the open or closed status of the monitoring circuit. The monitoring circuit traverses one or more of the solder joints between components being joined, such as a printed circuit board and an integrated circuit device. In certain embodiments, the inactive solder joints may be located within regions of the ball grid array that are predisposed to failure, such as at the periphery or corners of the printed circuit board, or proximate to regions that experience a broad range of operating temperatures. The failure of a solder joint within the monitoring circuit can be used to schedule maintenance of the ball grid array device prior to failure of an active solder joint.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

A test vehicle, along with methods for fabricating and using a test vehicle, are disclosed herein. In one example, a test vehicle is provided that includes a substrate, at least a first passive die mounted on the substrate, and at least a first test die mounted on the substrate. The first test die includes test circuitry configured to test continuity through solder interconnects formed between the substrate and the first passive die.

A test vehicle, along with methods for fabricating and using a test vehicle, are disclosed herein. In one example, a test vehicle is provided that includes a substrate, at least a first passive die mounted on the substrate, and at least a first test die mounted on the substrate. The first test die includes test circuitry configured to test continuity through solder interconnects formed between the substrate and the first passive die.

An apparatus and method for testing a circuit board included in a battery management system. The circuit board includes a first test point connected in common to one end of a first resistor, one end of a first capacitor and one end of a second resistor; a second test point connected in common to the other end of the second resistor and one end of a second capacitor; a third test point connected to the other end of the first resistor; and a fourth test point connected in common to the other end of the first capacitor and the other end of the second capacitor. The apparatus determines an open-circuit fault of at least one of the first capacitor and the second capacitor based on a first diagnosis voltage between the first and fourth test points and a second diagnosis voltage between the second and fourth test points.

Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.

Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.

A circuit board comprising a contacting arrangement, including three metal contacting regions, which are connected with one or more data links of the circuit board and in the case of contact with a communication interface of a test system enable a data exchange with a data memory of a circuit board.