Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices. Methods of fabricating such circuits and systems are also described.

An optical waveguide package includes a substrate including a first surface, a cladding on the first surface, and a core in the cladding. A first distance from the first surface of the substrate to a first incident port of a first core differs from a second distance from the first surface to a second incident port of a second core.

According to an aspect of the present disclosure, an edge coupler for a photonic chip is provided. The edge coupler includes a substrate having a top surface, a sealed cavity in the substrate, a waveguide core, and a back-end-of-line stack. The sealed cavity has varying depths relative to the top surface of the substrate. The waveguide core is over the sealed cavity. The back-end-of-line stack includes a side edge, an interlayer dielectric layer, and an assisting waveguide. The assisting waveguide is on the interlayer dielectric layer adjacent to the side edge. The assisting waveguide and the waveguide core have an overlapping arrangement with the sealed cavity in the substrate.

A semiconductor optical device includes a substrate including a waveguide made of silicon and a semiconductor layer joined to the substrate so as to overlap the waveguide and including a diffraction grating formed of a first semiconductor layer and a second semiconductor layer having different refractive indices. The waveguide includes a bent portion and a plurality of straight portions that are connected to each other by the bent portion and that extend straight. The first semiconductor layer and the second semiconductor layer are each made of a compound semiconductor. The second semiconductor layer is embedded in the first semiconductor layer and includes a plurality of portions arranged in a direction in which the plurality of straight portions extend. The diffraction grating is positioned above the plurality of straight portions.

A photonic integrated circuit (PIC) includes photonic components fabricated on the PIC. One of the photonic components includes an optical coupler configured to optically couple to an optical component. The optical coupler includes waveguide elements arranged in a 2-Dimensional array that is configured to provide a first mode having a first shape chosen to match a second shape of a second mode of the optical component.

Disclosed is a photonic integrated circuit (PIC) structure including: a first waveguide with a first main body and a first end portion, which is tapered; and a second waveguide with a second main body and a second end portion, which has two branch waveguides that are positioned adjacent to opposing sides, respectively, of the first end portion of the first waveguide and that branch out from the second main body, thereby forming a V, U or similar shape. The arrangement of the two branch waveguides of the second end portion of the second waveguide relative to the tapered first end portion of the first waveguide allows for mode matching conditions to be met at multiple locations at the interface between the waveguides, thereby creating multiple signal paths between the waveguides and effectively reducing the light signal power density along any one path to prevent or at least minimize any power-induced damage.

Thermal isolation elements are provided in wafer-bonded silicon photonics that include a photonic platform, including a heating element and an optical waveguide that are disposed between a first surface and a second surface (opposite to the first surface) of the photonic platform; a substrate, including a third surface and a fourth surface (opposite to the third surface); wherein the first surface of the photonic platform is bonded to the third surface of the substrate; and wherein a cavity is defined by a trench in one or more of: the first surface and extending towards, but not reaching, the second surface, and the third surface and extending towards, but not reaching, the fourth surface; wherein the cavity is filled with a gas of a known composition at a predefined pressure; and wherein the cavity is aligned with the optical waveguide and the heating element.

Methods for post-fabrication trimming of a silicon ring resonator are disclosed. Methods include fabricating a heating element, positioned within 2 microns of the silicon ring resonator, subjecting the silicon ring resonator to energetic ion implantation, and annealing the silicon ring resonator, using the heating element. The energetic ion implantation shifts a resonance of the silicon ring resonator towards the red side of the electro-magnetic spectrum. The annealing shifts the resonance of the silicon ring resonator towards the blue side of the electro-magnetic spectrum.

A photonic integrated circuit includes a substrate, an interconnection layer, and a plurality of silicon waveguides. The interconnection layer is over the substrate. The interconnection layer includes a seal ring structure and an interconnection structure surrounded by the seal ring structure. The seal ring structure has at least one recess from a top view. The recess concaves towards the interconnection structure. The silicon waveguides are embedded in the substrate.

A cavity substrate may have a directional optoelectronic transmission channel. The cavity substrate includes a support frame, a first dielectric layer on a first surface of the support frame, and a second dielectric layer on a second surface of the support frame. The support frame, the first dielectric layer and the second dielectric layer constitute a closed cavity having an opening on one side in the length direction of the substrate, a first circuit layer is arranged on the inner surface of the first dielectric layer facing the cavity, an electrode connected with an optical communication device is arranged on the first circuit layer, the electrode is electrically conducted with the first circuit layer, a second circuit layer is arranged on the outer surfaces of the first dielectric layer and the second dielectric layer, and the first circuit layer and the second circuit layer are communicated through a via column.