Aspects of the present disclosure are directed to fabrication of large-footprint chips having integrated photonic components comprising low-loss optical waveguides. The large footprint chips require the use of multiple reticles during fabrication. Stitching adjacent reticle fields seamlessly is accomplished by overlaying into adjacent reticle fields, tapering waveguide ends, and using strategically placed alignment marks in the die.

Methods for patterning of multi-depth layers for the fabrication of optical devices are provided. In one embodiment, a method is provided that includes disposing a resist layer over a device layer disposed over a top surface of a substrate, the device layer having a first portion and a second portion, patterning the resist layer to form a first resist layer pattern having a plurality of first openings and a second resist layer pattern having a plurality of second openings, and etching exposed portions of the device layer defined by the plurality of first openings and the plurality of second openings, wherein the plurality of first openings are configured to form at least a portion of a plurality of first structures within the optical device, and the plurality of second openings are configured to form at least a portion of a plurality of second structures within the optical device.

Structures for a waveguide bend and methods of fabricating a structure for a waveguide bend. A waveguide core has a first section, a second section, and a waveguide bend connecting the first section with the second section. The waveguide core includes a first side surface extending about an inner radius of the waveguide bend and a second side surface extending about an outer radius of the waveguide bend. A curved strip is arranged over the waveguide bend adjacent to the first side surface or the second side surface.

The disclosed structures and methods are directed to a chip for an optical gyroscope and methods of manufacturing of the chip for the optical gyroscope. The chip comprises a substrate, a waveguide having a first waveguide cladding layer and a waveguide core; and a ring resonator having a first ring cladding layer and a ring resonator core attached to the first ring cladding layer. A side wall of the ring resonator core forms an obtuse angle with an upper surface of the substrate. The method comprises depositing a first cladding layer on an upper surface of a silicon substrate; depositing a core layer; depositing a resist mask pattern to define a form of a ring resonator core and a form of a waveguide core; etching the core layer outside of the resist mask pattern; and stripping the resist mask pattern off.

Provided is an optical waveguide comprising a core surrounded by a cladding, wherein the core is in the shape of a trapezoid with sidewall angles between 60° and 85° and an opto-electronic circuit comprising the optical waveguide. Operational characteristics of the optical waveguide are shown to be superior to those of incumbent devices.

This method comprises: before bonding a substrate to a layer of encapsulated semiconductor material in which a first part of an optical component is produced, producing indented pads inside a buried layer of silicon oxide, with each of these pads comprising an embedded face that extends parallel to an interface between the buried layer and the layer of encapsulated semiconductor material to a predetermined depth inside the buried layer, with each of the embedded faces being made of a material different from silicon oxide; then thinning the buried layer in order to leave a residual silicon oxide layer on the layer of encapsulated semiconductor material, with this thinning comprising an operation involving thinning the buried layer, with this thinning stopping as soon as the embedded face of the pads is exposed.

A dicing system and methods may include a novel way to separate die on a wafer in preparation for packaging that results in smooth diced edges. This is specifically advantageous, but not limited to, edge-coupled photonic chips. This method etches from the front side of the wafer and dices from the back side of the wafer to create a complete separation of die. It creates an optically smooth surface on the front side of the wafer at the location of the optical device (waveguides or other) which enables direct mounting of adjacent devices with low coupling loss and low optical scattering. The backside dicing may be wider than the front side etch, so as to recess this sawed surface and prevent it from protruding outward, resulting in rough surfaces inhibiting a direct joining of adjacent devices.

A substrate of an optical electrical module is provided. The substrate includes a plurality of accommodating grooves and a reflective groove. The accommodating grooves respectively extend along a first direction. The reflective groove is connected with the accommodating grooves and extends along a second direction perpendicular to the first direction.

A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.

A semiconductor device is provided. The semiconductor device includes a silicon nitride waveguide in a first dielectric layer over a substrate. The semiconductor device includes a semiconductor waveguide in a second dielectric layer over the first dielectric layer. The first dielectric layer including the silicon nitride waveguide is between the second dielectric layer including the semiconductor waveguide and the substrate.