Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

A plurality of waveguide display substrates, each waveguide display substrate having a cylindrical portion having a diameter and a planar surface, a curved portion opposite the planar surface defining a nonlinear change in thickness across the substrate and having a maximum height D with respect to the cylindrical portion, and a wedge portion between the cylindrical portion and the curved portion defining a linear change in thickness across the substrate and having a maximum height W with respect to the cylindrical portion. A target maximum height D.sub.t of the curved portion is 10.sup.7 to 10.sup.6 times the diameter, D is between about 70% and about 130% of D.sub.t, and W is less than about 30% of D.sub.t.

A method for fabricating a photonic integrated circuit (PIC), where the method includes providing a first PIC die including a first optical component covered by a first dielectric layer; performing a location specific ion beam planarizing of the first dielectric layer to form a first planarized surface; providing a second PIC die including a second optical component covered by a second dielectric layer; performing a planarizing of the second dielectric layer to form a second planarized surface; and bonding the first planarized surface of the first PIC die to the second planarized surface of the second PIC die to form a three dimensional (3D) stacked PIC die.

The present disclosure provides a method for modification of surface of an initial optical fiber preform. The initial optical fiber preform is manufactured using at least one preform manufacturing process. The surface of the initial optical fiber preform is treated with 50-70 liters of chlorine per square meter of the surface of the initial optical fiber preform. The surface of the initial optical fiber preform is flame polished using a flame polishing module. The treatment of the surface of the initial optical fiber preform with chlorine and flame polishing of the surface of the initial optical fiber preform collectively converts the initial optical fiber preform into a modified optical fiber preform.

Method for preparing micro-optical structure on a film based on chemical mechanical polishing etching, combining photolithography technology with chemical mechanical polishing technology to make preparation and large-scale integration of large-size high-quality micro optical devices on-chip possible. The method comprises coating metal on film surface, selectively removing the metal film by photolithography (such as femtosecond laser selective ablation, ultraviolet photolithography, electron beam etching, ion beam etching, and reactive ion etching), chemical mechanical polishing, chemical corrosion or over polishing and other steps. Micro-optical devices on-chip prepared by the method have extremely high surface finish and extremely low optical loss. The method is applicable to preparing high-quality micro-optical structures (including but not limited to microdisc cavities, microring cavities, optical waveguides and coupled devices thereof) on various films on-chip (including but not limited to lithium niobate single crystal films, quartz films, silicon films, silicon dioxide films, diamond thin films, etc.).

An optical transceiver including a photonic integrated circuit component, an electric integrated circuit component and an insulating encapsulant is provided. The photonic integrated circuit component includes at least one optical input/output portion and at least one groove located in proximity of the at least one optical input/output portion. The electric integrated circuit component is disposed on and electrically connected to the photonic integrated circuit component.

The insulating encapsulant is disposed on the photonic integrated circuit component and laterally encapsulating the electric integrated circuit component. The at least one groove of the photonic integrated circuit component is revealed by the insulating encapsulant and is adapted for insertion of a photonic device.

A semiconductor-on-insulator (SOI) structure and a method for forming the SOI structure. The method includes forming a first dielectric layer on a first semiconductor layer. A second semiconductor layer is formed over an etch stop layer. A cleaning solution is provided to a first surface of the first dielectric layer. The first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. An index guiding layer may be formed over the second semiconductor layer. A third semiconductor layer is formed over the second semiconductor layer. A distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. A planarization process is performed on the third semiconductor layer to reduce the maximum distance.

A plurality of waveguide display substrates, each waveguide display substrate having a cylindrical portion having a diameter and a planar surface, a curved portion opposite the planar surface defining a nonlinear change in thickness across the substrate and having a maximum height D with respect to the cylindrical portion, and a wedge portion between the cylindrical portion and the curved portion defining a linear change in thickness across the substrate and having a maximum height W with respect to the cylindrical portion. A target maximum height D.sub.t of the curved portion is 10.sup.?7 to 10.sup.?6 times the diameter, D is between about 70% and about 130% of D.sub.t, and W is less than about 30% of D.sub.t.

Method for preparing micro-optical structure on a film based on chemical mechanical polishing etching, combining photolithography technology with chemical mechanical polishing technology to make preparation and large-scale integration of large-size high-quality micro optical devices on-chip possible. The method comprises coating metal on film surface, selectively removing the metal film by photolithography (such as femtosecond laser selective ablation, ultraviolet photolithography, electron beam etching, ion beam etching, and reactive ion etching), chemical mechanical polishing, chemical corrosion or over polishing and other steps. Micro-optical devices on-chip prepared by the method have extremely high surface finish and extremely low optical loss. The method is applicable to preparing high-quality micro-optical structures (including but not limited to microdisc cavities, microring cavities, optical waveguides and coupled devices thereof) on various films on-chip (including but not limited to lithium niobate single crystal films, quartz films, silicon films, silicon dioxide films, diamond thin films, etc.).

A grating for line-narrowing a laser beam that is outputted from a laser apparatus at a wavelength in a vacuum ultraviolet region may include: a grating substrate; a first aluminum metal film formed above the grating substrate, the first aluminum metal film having grooves in a surface thereof; and a first protective film formed by an ALD method above the first aluminum metal film.