Disclosed is a method for modeling measurement data over a substrate area and associated apparatus. The method comprises obtaining measurement data relating to a first layout; modeling a second model based on said first layout; evaluating the second model on a second layout, the second layout being more dense than said first layout; and fitting a first model to this second model according to the second layout.

A method for determining a process window of a patterning process based on a failure rate. The method includes obtaining a plurality of features printed on a substrate, grouping, based on a metric, the features into a plurality of groups, and generating, based on measurement data associated with a group of features, a base failure rate model for the group of features, wherein the base failure rate model identifies the process window related to the failure rate of the group of features. The method can further include generating, using the base failure rate model, a feature-specific failure rate model for a specific feature, wherein the feature-specific failure rate model identifies a feature-specific process window such that an estimated failure rate of the specific feature is below a specified threshold.

A system and method for shaping a film on a partial field including determining an initial contact point. Receiving information about: a partial field of a substrate; and an edge of a patternable area of the substrate. Determining a chord that connects intersection vertices of the partial field and the edge. Determining coordinates of a bisecting line, wherein the bisecting line bisects the chord, and the bisecting line is orthogonal to the chord. Determining an initial contact point range on the bisecting line in which a template and formable material on the substrate contact each other. Contacting the formable material in the partial field on the substrate with the template at an initial contact point within the initial contact point range.

A method involving obtaining a resist deformation model for simulating a deformation process of a pattern in resist, the resist deformation model being a fluid dynamics model configured to simulate an intrafluid force acting on the resist, performing, using the resist deformation model, a computer simulation of the deformation process to obtain a deformation of the developed resist pattern for an input pattern to the resist deformation model, and producing electronic data representing the deformation of the developed resist pattern for the input pattern.

A method for generating metrology sampling scheme for a patterning process, the method including: obtaining a parameter map of a parameter of a patterning process for a substrate; decomposing the parameter map to generate a fingerprint specific to an apparatus of the patterning process and/or a combination of apparatuses of the patterning process; and based on the fingerprint, generating a metrology sampling scheme for a subsequent substrate at the apparatus of the patterning process and/or the combination of apparatuses of the patterning process, wherein the sampling scheme is configured to distribute sampling points on the subsequent substrate so as to improve a metrology sampling density.

Multilayered product structures are formed on substrates by a combination of patterning steps, physical processing steps and chemical processing steps. An inspection apparatus illuminates a plurality of target structures and captures pupil images representing the angular distribution of radiation scattered by each target structure. The target structures have the same design but are formed at different locations on a substrate and/or on different substrates. Based on a comparison of the images the inspection apparatus infers the presence of process-induced stack variations between the different locations. In one application, the inspection apparatus separately measures overlay performance of the manufacturing process based on dark-field images, combined with previously determined calibration information. The calibration is adjusted for each target, depending on the stack variations inferred from the pupil images.

This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.

Embodiments of the present disclosure relate to a metrology method and system for critical dimensions based on a dispersion relation in momentum space. The method comprises: establishing, in accordance with parameters of incident light and a modeled geometric topography of the target to be measured, a simulation dataset associated with a dispersion curve of the target to be measured in momentum space; training a neural-network-based prediction model based on the simulation dataset; obtaining, based on an actual measurement of the target to be measured by incident light, a dispersion relation pattern of the target to be measured in momentum space, wherein the dispersion relation pattern at least indicates a dispersion curve associated with the critical dimensions of the target to be measured; extracting, based on the dispersion relation pattern, features related to the dispersion curve from the dispersion relation pattern via the trained prediction model, to determine an estimated value associated with at least one critical dimension of the target to be measured. According to the method disclosed herein, at least one critical dimension is measured in a more efficient, economical and accurate way.

A preparation method (100) for a three-dimensional micro-nano morphological structure manufactured by a laser direct writing lithography machine, comprising: step 110, providing a three-dimensional model diagram; step 120, dividing the three-dimensional model diagram in a height direction to obtain at least one height interval; and step 130, projecting the three-dimensional model diagram onto a plane to obtain a mapping relationship, wherein the mapping relationship comprises coordinates, on the plane, corresponding to each point on the three-dimensional model diagram, and wherein the height of each point on the three-dimensional model diagram corresponds to a height value in a corresponding height interval; and making the mapping relationship correspond to an exposure dose according to the mapping relationship, and performing lithography on the basis of the exposure dose. Any three-dimensional micro-nano morphological structure can be obtained. Further disclosed is a three-dimensional micro-nano morphology structure manufactured by a laser direct writing lithography machine.

Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.