A power down detection circuit that may detect a supply voltage decrease more accurately is provided. The power down detection circuit includes a BGR circuit generating a reference voltage VREF, a resistance division circuit generating a first internal voltage VCC_DIV1 and a second internal voltage VCC_DIV2 based on a supply voltage VCC, a first comparator outputting a reset signal PDDRST when detecting VCC_DIV1<VREF, a second comparator outputting a switching signal SEL when detecting VCC_DIV2<VREF, a charging pump circuit generating a boosted voltage VXX based on the supply voltage VCC, and a switching circuit switching an operating voltage supplied to the BGR circuit to the supply voltage VCC or the boosted voltage VXX based on the switching signal SEL.

A random code generator includes a power source, a sensing circuit, a first memory cell and a second memory cell. A first terminal of the first memory cell is connected with the power source. A second terminal of the first memory cell is connected with the sensing circuit. A first terminal of the second memory cell is connected with the power source. A second terminal of the second memory cell is connected with the sensing circuit. The power source provides a supplying voltage to both the first memory cell and the second memory cell during an enrollment. A random code is then determined according to the resistance difference between the first memory cell and the second memory cell after the enrollment.

A voltage generation circuit may include: a first transistor coupled to an internal supply voltage terminal, and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to a first reference voltage generated based on an external supply voltage. The voltage generation circuit may limit a variation in level of a second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.

The present document relates to Single Inductor Dual Input (SIDI) buck power converters. More specifically, a dual input power converter may comprise an inductor, a first high-side switching element, a second high-side switching element, and a low-side switching element. The inductor may be coupled between an intermediate node and an output of the dual input power converter. The first high-side switching element may be coupled between a first input of the dual input power converter and the intermediate node. The second high-side switching element may be coupled between a second input of the dual input power converter and the intermediate node. The low-side switching element may be coupled between the intermediate node and a reference potential.

A power supply circuit included in a computer system regulates a power supply voltage using an input power supply. During startup, the power supply circuit uses a first reference voltage that is generated using the input power supply to regulated the power supply voltage. After a period of time has elapsed, the power supply circuit switches to using a more accurate second reference voltage that is generated using the regulated power supply voltage.

A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.

Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

An amplitude shift keying (ASK) modulation system includes a linear regulator circuit powered by input direct current (DC) power at a first voltage level and that generates regulated DC power at a second voltage level tracking the first voltage level. The system also includes an intermediate DC power switching circuit that receives a digital data signal and selectively couples an intermediate power node with the input DC power at the first voltage level when the digital data signal represents a first binary value, and with the regulated DC power at the second voltage level when the digital data signal represents a second binary value. The ASK modulation system also includes a radio frequency (RF) driver circuit powered by intermediate DC power received at the intermediate power node and that delivers RF output power representative of the digital data signal to a load at an RF carrier frequency.

A reference voltage generation circuit may include: a first reference current path formed through a first node and a first transistor; a second reference current path formed through a second node and a second transistor; a first feedback loop configured to feed a first current back to the first and second reference current paths such that voltage levels of the first and second nodes are kept the same; and a second feedback loop configured to control the currents flowing through the first and second transistors according to a second current.

A controller for a power converter includes a first input node receiving a sensing signal that indicates an output signal of the power converter, a second input node receiving an external signal that indicates a target value for a load, and a feedback signal generator generating a first feedback signal in response to the sensing signal and the external signal. The feedback signal generator uses a first feedback path with a first gain value when the power converter operates in a first mode and uses a second feedback path when the power converter operates in a second mode. The feedback signal generator includes a gain adjusting circuit configured to decrease a gain value of the second feedback path from the first gain value to a second gain value at a plurality of times when the power converter operates in the second mode