A current mirror circuit includes a current output terminal, a first transistor, a second transistor, and a digital-to-analog converter (DAC). The first transistor includes a first terminal coupled to a power rail, a second terminal coupled to a current source, and a third terminal coupled to the current source. The second transistor includes a first terminal coupled to the power rail, a second terminal coupled to the second terminal of the first transistor, and a third terminal coupled to the current output terminal. The DAC includes an output terminal coupled to the second transistor.

A switching regulator may be used to generate an output voltage from an input voltage. The switching regulator includes; an inductor including a first terminal and a second terminal that passes an inductor current from the first terminal to the second terminal, a first switch that applies the input voltage to the first terminal when turned ON, a second switch that applies a ground potential to the first terminal when turned ON, a feedback circuit configured to estimate a load receiving the output voltage, detect when the inductor current reaches an upper bound or a lower bound, and adjust the lower bound based on the estimated load, and a switch driver configured to control the first switch and the second switch, such that the inductor current is between the upper bound and the lower bound in response to at least one feedback signal provided by the feedback circuit.

Voltage-to-current converters that include two current mirrors are disclosed. In an example voltage-to-current converter each current mirror is a complementary current mirror in that one of its input and output transistors is a P-type transistor and the other one is an N-type transistor. Such voltage-to-current converters may be implemented using bipolar technology, CMOS technology, or a combination of bipolar and CMOS technologies, and may be made sufficiently compact and accurate while operating at sufficiently low voltages and consuming limited power.

Described is an apparatus which comprises: a current source to generate a current having AC and DC components; a current-to-voltage converter to convert the current or a copy of the current to a voltage proportional to a resistance, the voltage having AC and DC components that correspond to the AC and DC components of the current; a first sample-and-hold circuit to sample and filter the AC component from the voltage and to provide an output voltage with the DC component; a second sample-and-hold circuit to sample the output voltage; a voltage-to-current converter to convert the sampled output voltage to a corresponding current; and an amplifier to receive the output voltage.

The present invention provides a voltage regulator including a voltage control circuit and a current control circuit. The voltage control circuit is configured to receive an output voltage of the voltage regulator to generate a first current to an output terminal of the voltage regulator; and the current control circuit is configured to generate a second current to the output terminal of the voltage regulator according to an output current of the voltage regulator, wherein the output current is generated according to the first current and the second current.

Disclosed is a reference voltage generating circuit including a bandgap reference voltage generating circuit, a voltage controlled current source circuit, a current mirror circuit, an input voltage generating circuit, and a voltage controlled voltage source circuit. The bandgap reference voltage generating circuit generates a bandgap reference voltage. The voltage controlled current source circuit generates a reference current according to the bandgap reference voltage. The current mirror circuit generates a mirrored current according to the reference current. The input voltage generating circuit determines an input voltage according to the mirrored current. The voltage controlled voltage source circuit generates a reference voltage according to the input voltage. Accordingly, the reference voltage is generated with voltage-to-current conversion and voltage-to-voltage conversion so that the mirrored current can be accurate without being affected by the reference voltage and the reference voltage itself can be accurate.

The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.

A current mirror circuit includes a current output terminal, a first transistor, a second transistor, and a digital-to-analog converter (DAC). The first transistor includes a first terminal coupled to a power rail, a second terminal coupled to a current source, and a third terminal coupled to the current source. The second transistor includes a first terminal coupled to the power rail, a second terminal coupled to the second terminal of the first transistor, and a third terminal coupled to the current output terminal. The DAC includes an output terminal coupled to the second transistor.

A memory system having a temperature effect compensation mechanism is provided. The memory system may include a plurality of memory cells, where the memory cells are organized in an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The plurality of memory cells may have an operating temperature range. The memory system may also include a temperature-dependent biasing circuit that is configured to reduce a biasing voltage to the plurality of memory cells when the temperature of the array is at or near an upper end of the operating temperature range and increase the biasing voltage to the plurality of memory cells when the temperature of the array is at or near a lower end of the operating temperature range.

A low dropout linear voltage regulator is provided. In the low dropout linear voltage regulator, a power transistor has a source connected to a power source, a gate connected to an output terminal of an error amplifier, a drain connected to an output terminal of the low dropout linear voltage regulator. A dynamic Miller compensation network has a first terminal connected to the output terminal of the error amplifier, a second terminal connected to the output terminal of the low dropout linear voltage regulator. A controller has a first terminal connected to the gate of the power transistor, and a second terminal connected to a third terminal of the Miller compensation network. The controller is configured to detect a current at the output terminal of the low dropout linear voltage regulator and generate control signals according to the current to control connection and disconnection of each second resistance-capacitance branch in the dynamic Miller compensation network.