A regulator for providing a load current at a regulator output voltage to a load at an output of the regulator is described. The regulator has a differential input stage to provide a differential output voltage based on a reference voltage and based on the regulator output voltage. Furthermore, the regulator has an output driver to generate a control signal based on the differential output voltage. In addition, the regulator has a pass transistor to provide the load current in dependence of the control signal. The regulator also has clamping circuitry to sense an overvoltage indication which indicates that the pass transistor is being turned off. Furthermore, the clamping circuitry clamps the differential output voltage to a clamping voltage, if the overvoltage indication indicates that the pass transistor is being turned off.

A power control device includes: an output voltage controller to control the output voltage of a power supply circuit based on a feedback voltage obtained by dividing the output voltage with voltage dividing resistors; and an overvoltage protection circuit to protect against an overvoltage in the output voltage. The overvoltage protection circuit includes: an output voltage detector to detect whether the output voltage has risen above an output voltage threshold value; and a feedback voltage detector to detect whether the feedback voltage has fallen to or below a feedback voltage threshold value. The overvoltage protection circuit continues or stops operation of the output voltage controller based on a first detection output from the output voltage detector and a second detection output from the feedback voltage detector.

In described examples of methods and control circuitry to control a power conversion system, a regulator circuit is coupled to provide switching control signals according to a regulation signal to operate a plurality of converter switches to generate a voltage signal at a switching node. A compensation sense circuit is coupled to provide a compensation pulse signal having a duty cycle that represents a percentage of time that a current flowing through the switching node is above a threshold value. A current compensation circuit adjusts the regulation signal according to the compensation pulse signal.

An apparatus includes a first switch coupled between a first voltage source and input/output (I/O) circuitry of a memory device, wherein the first voltage source is to supply power to core memory circuitry of the memory device. A second switch is coupled between a second voltage source and the I/O circuitry. Control logic is coupled with the first and second switches and to cause the second switch to be activated to permit current to flow from the second voltage source to the I/O circuitry. The control logic, in response to detecting a current draw from the I/O circuitry that satisfies a first threshold criterion, causes the first switch to be activated.

This application relates to a circuit for generating an output voltage and regulating the output voltage to a target voltage. The circuit includes a switchable voltage divider circuit configured to generate a feedback voltage that is a variable fraction of the output voltage, an error amplifier stage configured to generate a control voltage on the basis of a reference voltage and the variable fraction of the output voltage, a buffer stage configured to generate the output voltage on the basis of the control voltage, and a charge injection circuit configured to inject charge at an intermediate node between the error amplifier stage and the buffer stage to thereby modify the control voltage generated by the error amplifier stage. The application further relates to a method of operating such circuit.

A device and method that includes a shunt regulator of a universal serial bus (USB) compatible power supply device is disclosed. The shunt regulator includes an amplifier with an output, a first input, and a second input. The shunt regulator also includes a current digital-to-analog converter (DAC) that is coupled to the first input of the amplifier and a voltage bus node. The current DAC adjusts a sink or a source current delivered at the first input of the amplifier to regulate a programmable output voltage (Vbus) in the USB-compatible power supply device. The current delivered by the DAC is responsive to receipt of a digital code indicative of a programmable power supply command specifying the Vbus to be delivered by the USB-compatible power supply device on the voltage bus node.

In one form, a data transmission system includes transmission and reception circuits. The transmission circuit includes a first driver having an input for receiving a first transmit data signal, an output, a positive power supply terminal for receiving an input/output (I/O) power supply voltage, and a negative terminal for receiving an I/O ground voltage, a second driver having an input for receiving the I/O power supply voltage, an output, and a positive power supply terminal for receiving the I/O power supply voltage, and a third driver having an input for receiving the I/O ground voltage, an output, and a negative power supply terminal coupled to the I/O ground voltage. The reception circuit forms a reference voltage based an average of signal content below a predetermined frequency of outputs of the second and third drivers, and receives a signal from the output of the first driver using the reference voltage.

A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

A voltage regulating circuit provides a feedback voltage and an output voltage based on a power voltage. The voltage regulating circuit includes a reference voltage generator and a compensating circuit. The reference voltage generator receives the power voltage, produces the feedback voltage, and includes an impedance having first and second terminals. The second terminal is coupled to a ground voltage and a first current flows through the impedance at the first terminal to produce the feedback voltage. The compensating circuit includes a negative threshold voltage (NVT) transistor having a source terminal, a drain terminal and a gate terminal. The source terminal receives a power voltage, the drain terminal is connected to the gate terminal and coupled to the first terminal of the impedance through a path to add a second current to the first current when the NVT transistor is turned on under an operational condition at the FF corner.

A cascaded thin-oxide N-Well voltage steering circuit includes a reference voltage generator that outputs a reference voltage within a range of first and second supply voltages, a first voltage steering circuit that outputs a higher available one of the reference voltage and the second supply voltage as an interim voltage, and a second voltage steering circuit that outputs a higher available one of the first voltage and the interim voltage at an output of the second voltage steering circuit. The interim voltage is applied to N-wells of PMOS transistors of the first voltage steering circuit. The output of the second voltage steering circuit is applied to N-wells of PMOS transistors of the second voltage steering circuit. The output of the second voltage steering circuit may also be applied to N-wells of PMOS transistors of other circuitry. The cascaded thin-oxide N-Well voltage steering circuit may consist substantially of thin-oxide PMOS transistors.