The present disclosure provide an electronic device. The electronic device includes a voltage generator and a low drop-out (LDO) circuit. The voltage generator has an input and an output. The LDO circuit has an input electrically connected to the output of the voltage generator. The voltage generator includes a first voltage regulator having a first terminal and a second terminal. The first terminal of the first voltage regulator is electrically connected to the output of the voltage generator.

A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.

A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.

A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and has an output at which an amplified feedback signal is provided to both the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first LDO stage or the second LDO stage. A current limit circuit includes a sense FET having a gate coupled to the gate of the LDO pass FET, a drain voltage replication circuit coupled between the drains of the pass FET and sense FET to replicate the pass FET drain voltage so that the sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.

A low dropout (LDO) voltage regulator includes a first LDO stage that receives a first supply voltage and is active during a first time interval and a second LDO stage that receives a second supply voltage and is active during a second time interval. An operational amplifier receives a feedback voltage based on the LDO output voltage and has an output at which an amplified feedback signal is provided to both the first and second LDO stages. A compensation capacitor is selectively coupled between the operational amplifier and either the first LDO stage or the second LDO stage. A current limit circuit includes a sense FET having a gate coupled to the gate of the LDO pass FET, a drain voltage replication circuit coupled between the drains of the pass FET and sense FET to replicate the pass FET drain voltage so that the sense current is indicative of load current when the pass FET is in a linear region, and a current comparator to compare the sense current to a predetermined current level.

A voltage regulation circuit, device, and method are disclosed, which relate to the field of electronic technologies, to reduce a voltage regulation time, and improve a system response and user experience. The voltage regulation circuit (1) includes: a first power supply circuit (11), configured to receive a voltage setting signal (S.sub.SET), and output a first supply voltage (V1) and a second reference voltage (V.sub.REF2) according to the voltage setting signal (S.sub.SET) and a difference between a first feedback voltage (V.sub.F1) and a second feedback voltage (V.sub.F2), where the first feedback voltage (V.sub.F1) is used to indicate the first supply voltage (V1), and the second feedback voltage (V.sub.F2) is used to indicate a second supply voltage (V2); and a second power supply circuit (12), configured to output the second supply voltage (V2) based on the second reference voltage (V.sub.REF2).

A voltage regulation circuit, device, and method are disclosed, which relate to the field of electronic technologies, to reduce a voltage regulation time, and improve a system response and user experience. The voltage regulation circuit (1) includes: a first power supply circuit (11), configured to receive a voltage setting signal (S.sub.SET), and output a first supply voltage (V1) and a second reference voltage (V.sub.REF2) according to the voltage setting signal (S.sub.SET) and a difference between a first feedback voltage (V.sub.F1) and a second feedback voltage (V.sub.F2), where the first feedback voltage (V.sub.F1) is used to indicate the first supply voltage (V1), and the second feedback voltage (V.sub.F2) is used to indicate a second supply voltage (V2); and a second power supply circuit (12), configured to output the second supply voltage (V2) based on the second reference voltage (V.sub.REF2).

Described embodiments include a voltage regulator circuit comprising an output voltage terminal configured to be coupled to a load that draws a load current, first and second amplifiers, and first, second, third, fourth and fifth transistors. The embodiment also includes a dynamic R-C network coupled between the third amplifier input and the seventh transistor current terminal, wherein the dynamic R-C network includes capacitors and MOS-based resistors, a third amplifier having a fourth amplifier input and a third amplifier output, wherein the fourth amplifier input is coupled to the output voltage terminal, and a capacitor that is coupled between the output voltage terminal and the fourth amplifier input.