An apparatus, system, and method for voltage regulator (VR) control are provided. An apparatus can include first, second, and third comparators configured to determine whether a load voltage (VLOAD) drops below a lower non-linear control (NLC) threshold, drops below a lower linear control (LC) threshold, and exceeds an upper LC threshold, respectively. The apparatus can include power gates (PGs) configured to adjust an output voltage (VOUT) based on a provided power gate (PG) code. The apparatus can include voltage regulator (VR) controller circuitry comprising synchronous LC circuitry and asynchronous NLC circuitry, the LC circuitry configured to increment or decrement the PG code responsive to the VLOAD dropping below the LC threshold and exceeding the upper LC threshold, respectively, and the NLC circuitry configured to increase the PG code based on a number of consecutive NLC droop events and responsive to the VLOAD dropping below the lower NLC threshold.

Embodiments disclosed herein relate to a low-voltage dropout regulator and more specifically to improving a power supply rejection ratio (PSRR) of the low dropout voltage regulator. The low dropout voltage regulator may be used to generate various voltages for integrated circuits of an electronic device. In some cases, a P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) voltage regulator may be used. However, the PMOS LDO may not provide a sufficient PSRR or reduction in supply noise. To address these issues, an N-type metal-oxide-semiconductor (NMOS) LDO voltage regulator having an NMOS pass transistor may be used. The NMOS LDO may provide a lower impedance than the PMOS LDO. Further, the NMOS LDO may provide an increased bandwidth and consume a smaller physical area than the PMOS LDO.

Embodiments disclosed herein relate to a low-voltage dropout regulator and more specifically to improving a power supply rejection ratio (PSRR) of the low dropout voltage regulator. The low dropout voltage regulator may be used to generate various voltages for integrated circuits of an electronic device. In some cases, a P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) voltage regulator may be used. However, the PMOS LDO may not provide a sufficient PSRR or reduction in supply noise. To address these issues, an N-type metal-oxide-semiconductor (NMOS) LDO voltage regulator having an NMOS pass transistor may be used. The NMOS LDO may provide a lower impedance than the PMOS LDO. Further, the NMOS LDO may provide an increased bandwidth and consume a smaller physical area than the PMOS LDO.

The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (M.sub.O) having a source coupled to an input voltage (Vin); a noise cancelling transistor (M.sub.D) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (M.sub.SF) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.

A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (M.sub.O) having a source coupled to an input voltage (Vin); a noise cancelling transistor (M.sub.D) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (M.sub.SF) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.

Embodiments relate to digital low-dropout (DLDO) with fast feedback and optimized frequency response. Certain embodiments may relate more particularly to ferroelectric memory circuit configurations. For example, a low dropout regulator may include a first circuit path configured to regulate an input voltage to an output voltage at a load, wherein the first path comprises a first transistor. The apparatus may also include a second circuit path configured to feed back an error signal based on the input voltage and the output voltage, wherein the second circuit path comprises an error amplifier.

A voltage regulator circuit is disclosed. The voltage regulator includes a feedback circuit configured to generate a feedback signal based on a voltage level present on a regulated power supply node. A comparison circuit is arranged to generate an error signal based on the feedback signal and a reference voltage level. A compensation circuit is configured to modify the error signal, based on a routing impedance coupled between the regulated supply voltage node and a load circuit, to generate a control circuit. An output circuit of the voltage regulator is configured to source current to the regulated power supply node based on the control signal.

A voltage regulator circuit is disclosed. The voltage regulator includes a feedback circuit configured to generate a feedback signal based on a voltage level present on a regulated power supply node. A comparison circuit is arranged to generate an error signal based on the feedback signal and a reference voltage level. A compensation circuit is configured to modify the error signal, based on a routing impedance coupled between the regulated supply voltage node and a load circuit, to generate a control circuit. An output circuit of the voltage regulator is configured to source current to the regulated power supply node based on the control signal.