A discharge circuit for a diode reverse leakage current includes an input positive terminal, an input negative terminal, an output positive terminal coupled to the input positive terminal, an output negative terminal coupled to the input negative terminal, a diode and a current source device. The diode has an anode terminal coupled to the input positive terminal and a cathode terminal coupled to the output positive terminal. The current source device has a first end coupled to the anode terminal of the diode and a second end coupled between the input and output negative terminals. The voltage difference across the current source device is reduced by less than about 1 V when input voltage is switched off. The current source device continues to operate when the input voltage is normal. As P=VI, the loss is proportional to the input voltage, therefore achieving the objective of low loss.

A reference voltage generator includes a depletion NMOS transistor of a first conductivity type for causing a constant current to flow, and an enhancement NMOS transistor of the first conductivity type diode-connected to the depletion NMOS transistor to generate a reference voltage. A resistor surrounds the periphery of the depletion NMOS transistor and the periphery of the enhancement NMOS transistor. A diode is connected in series to a constant current source and provides a voltage that controls current flowing through the resistor when the environment temperature is lower than a preset temperature. The reference voltage generator can operate under a given preset temperature environment because a voltage consumed in the resistor becomes approximately constant in accordance with the voltage provided from the diode.

An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Embodiments of power source circuits and methods for operating a power source circuit are described. In one embodiment, a method for operating a power source circuit involves receiving at the power source circuit at least one digital signal from a feedback loop and increasing or decreasing an output power signal of the power source circuit in response to the at least one digital signal. Other embodiments are also described.

A tracking current sense system is described that includes a current source and a current control device. The current source alternatively and substantially replicates a first current flowing through a first switch and a second current flowing through a second switch. The current control device configures the current source to alternate between replicating the first current and the second current.

Provided is a reference voltage circuit capable of outputting, with a low voltage and low current consumption, a voltage that is less liable to change due to a temperature change, and has a low GND terminal reference voltage. The reference voltage circuit includes a first NMOS transistor and a second NMOS transistor connected by a current mirror circuit, the first NMOS transistor having a gate and a drain connected to each other via a first resistor, the second NMOS transistor having a gate connected to the drain of the first NMOS transistor, and a source connected to a GND terminal via a second resistor, the second NMOS transistor having a threshold voltage lower than a threshold voltage of the first NMOS transistor, in which a reference voltage is output from the source of the second NMOS transistor.

Provided is a reference voltage circuit capable of outputting, with a low voltage and low current consumption, a voltage that is less liable to change due to a temperature change, and has a low GND terminal reference voltage. The reference voltage circuit includes a first NMOS transistor and a second NMOS transistor connected by a current mirror circuit, the first NMOS transistor having a gate and a drain connected to each other via a first resistor, the second NMOS transistor having a gate connected to the drain of the first NMOS transistor, and a source connected to a GND terminal via a second resistor, the second NMOS transistor having a threshold voltage lower than a threshold voltage of the first NMOS transistor, in which a reference voltage is output from the source of the second NMOS transistor.