This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

A voltage reference circuit is provided that includes a first circuit, a second circuit and a third circuit. The first circuit has a first MOS transistor pair and the second circuit has a second MOS transistor pair. The first circuit is configured to provide a first voltage component that changes at a first rate having a first slope as a temperature to which the voltage reference circuit is subjected changes. The second circuit is configured to provide a second voltage component that changes at a second rate having a second slope as the temperature changes. The third circuit is configured to use the first voltage component and the second voltage component to generate the reference voltage component that changes at a fifth rate having a fifth slope as the temperature changes. The fifth slope is substantially equal to zero to promote insensitivity of the reference voltage component to temperature changes.

A voltage reference circuit is provided that includes a first circuit, a second circuit and a third circuit. The first circuit has a first MOS transistor pair and the second circuit has a second MOS transistor pair. The first circuit is configured to provide a first voltage component that changes at a first rate having a first slope as a temperature to which the voltage reference circuit is subjected changes. The second circuit is configured to provide a second voltage component that changes at a second rate having a second slope as the temperature changes. The third circuit is configured to use the first voltage component and the second voltage component to generate the reference voltage component that changes at a fifth rate having a fifth slope as the temperature changes. The fifth slope is substantially equal to zero to promote insensitivity of the reference voltage component to temperature changes.

A reference voltage generating circuit including a bandgap reference circuit generating a bandgap reference voltage, and a filter circuit smoothing the bandgap reference voltage. The bandgap reference circuit is configured to generate the bandgap reference voltage having a first voltage value when a clock signal is in a first logic level, and to generate the bandgap reference voltage having a second voltage value when the clock signal is in a second logic level. The filter circuit includes a first capacitive element charged with the bandgap reference voltage having the first voltage value in the first clock cycle, a second capacitive element charged with the bandgap reference voltage having the second voltage value in the first clock cycle, a third capacitive element charged with the bandgap reference voltage, and a fourth capacitive element.

A reference voltage generating circuit including a bandgap reference circuit generating a bandgap reference voltage, and a filter circuit smoothing the bandgap reference voltage. The bandgap reference circuit is configured to generate the bandgap reference voltage having a first voltage value when a clock signal is in a first logic level, and to generate the bandgap reference voltage having a second voltage value when the clock signal is in a second logic level. The filter circuit includes a first capacitive element charged with the bandgap reference voltage having the first voltage value in the first clock cycle, a second capacitive element charged with the bandgap reference voltage having the second voltage value in the first clock cycle, a third capacitive element charged with the bandgap reference voltage, and a fourth capacitive element.

In an embodiment, an electronic device includes a first amplifier having a non-inverting input configured to receive a reference voltage and an inverting input coupled to a first output node, where the first amplifier is configured to produce a first output voltage at the first output node. The electronic device also includes a second amplifier having a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to a second output node via a second resistor, where the second amplifier is configured to produce a second output voltage at the second output node.

In an embodiment, an electronic device includes a first amplifier having a non-inverting input configured to receive a reference voltage and an inverting input coupled to a first output node, where the first amplifier is configured to produce a first output voltage at the first output node. The electronic device also includes a second amplifier having a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to a second output node via a second resistor, where the second amplifier is configured to produce a second output voltage at the second output node.

A fluid sample system includes a control system that operates in the hazardous area and controls one or more valves and optionally receives outputs from one or more transducers and optionally one or more sensors. The fluid sample system includes components that operate in a hazardous area and includes a control system that operates in the hazardous area and that controls one or more electrical devices. The control system communicates across a barrier with a system on a safe side of the barrier with as few as two intrinsically safe couplings including a single pneumatic coupling and a communication link coupling. The control system includes an intrinsically safe voltage boost circuit.

A family of bandgap embodiments are disclosed herein, capable of operating with very low currents and low power supply voltages, using neither any custom devices nor any special manufacturing technology, and fabricated on mainstream standard digital CMOS processes. As such, manufacturing cost can be kept low, manufacturing yields of digital CMOS system-on-a-chip (SOC) that require a reference can be kept optimal, and manufacturing risk can be minimized due to its flexibility with respect to fabrication process node-portability. Although the embodiments disclosed herein use novel techniques to achieve accurate operations with low power and low voltage, this family of bandgaps also uses parasitic bipolar junction transistors (BJT) available in low cost digital CMOS process to generate proportional and complementary to absolute temperature (PTAT and CTAT) voltages via the base-emitter voltage (V.sub.EB) of BJTs and scaling V.sub.EB differential pairs to generate the BJTs thermal voltage (V.sub.T).