Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

An arbitrary waveform sequencer device for playing a list of at least a first and a second arbitrary waveform file in a sequence is provided. The arbitrary waveform sequencer device comprises a list increment condition control unit configured to control an increment from the first to the second arbitrary waveform file as a function of an increment condition, and a transition control unit configured to control a timing of the increment.

The present invention provides an arbitrary waveform generator based on instruction architecture. To deal with the feature that the instructions and waveform data of the AWG are coupled in the prior art, an instruction set based waveform synthesis controller is employed, and substitutes for the sequence wave generator in the present invention, i.e. an arbitrary waveform generator based on instruction architecture. Thus the time-sharing scheduling in reading the waveform synthesis instruction and the segment waveform data is realized, and the complexity of the hardware is reduced, so that the AWG in present invention can synthesize and generate a complex sequence wave rapidly and efficiently.

A DDS circuit includes a phase accumulator circuit. The phase accumulator circuit includes a clock input being configured to receive a clock signal. The phase accumulator circuit includes a frequency tuning register configured to receive a frequency tuning word (FTW), and a phase shift register configured to receive a phase shift word (PSW). The phase accumulator circuit also includes a phase increment sub-circuit configured to increment a phase signal output by the phase accumulator circuit by a predetermined phase increment based on the clock signal and/or based on the FTW. The phase accumulator circuit further includes a feedback path configured to feed back the phase signal to the phase increment sub-circuit. The phase accumulator circuit further includes a phase correction sub-circuit configured to adapt the phase signal fed back to the phase increment sub-circuit based on the phase shift word.

A numerically controlled oscillator system for maintaining a consistent phase reference while switching data rates may include a numerically controlled oscillator (NCO) circuit. The NCO circuit may include a phase accumulator, a phase-to-signal mapping circuit, and a first free-running counter. The phase accumulator may receive a new phase value as an input in response to an update signal. The phase-to-signal mapping circuit may map a value from the phase accumulator to a periodic signal. The first free-running counter may continue counting, without being reset, while the numerically controlled oscillator system is switching digital data rates. The first free-running counter may be configured to provide the new phase value to the phase accumulator using a representation of a counter value of the first free-running counter and a frequency tuning word defined by a representation of a frequency of the periodic signal.

A numerically controlled oscillator system for maintaining a consistent phase reference while switching data rates may include a numerically controlled oscillator (NCO) circuit. The NCO circuit may include a phase accumulator, a phase-to-signal mapping circuit, and a first free-running counter. The phase accumulator may receive a new phase value as an input in response to an update signal. The phase-to-signal mapping circuit may map a value from the phase accumulator to a periodic signal. The first free-running counter may continue counting, without being reset, while the numerically controlled oscillator system is switching digital data rates. The first free-running counter may be configured to provide the new phase value to the phase accumulator using a representation of a counter value of the first free-running counter and a frequency tuning word defined by a representation of a frequency of the periodic signal.

The measurement circuit includes a clock input, a frequency converter circuit, and a first signal generator circuit. The clock input is configured to receive a reference clock signal. The first signal generator circuit includes a first clock generator circuit configured to generate a first clock signal having an adaptable frequency based on the reference clock signal. The first signal generator circuit further includes a first direct digital synthesizer (DDS) circuit configured to generate a local oscillator (LO) signal based on the first clock signal and based on an adaptable frequency tuning word (FTW) of the first DDS circuit. The adaptable frequency of the first clock signal and the adaptable FTW of the first DDS circuit are configured such that an IF signal is free of spurs emitted by the first DDS circuit at least in a predetermined frequency band.

Systems and methods are provided for generating a phase compensated numerically controlled signal using a fixed-point algorithm. In one example, a method includes receiving, at a downhole device, parameters including an input frequency and a compensation value. The method further includes converting, based on the parameters, the input frequency to a delta phase value. The method also includes calculating, with the downhole device, an accumulation error for a digital signal. In response to determining that the accumulation error is greater than or equal to the compensation value, the method removes the accumulation error from the digital signal to generate an output signal.

The present invention provides a frequency synthesizer that is switchable at a high speed and includes a few unnecessary frequency components in an output frequency signal. In a frequency synthesizer 1, a DDS 2 operates based on a clock signal to generate a reference frequency signal with a predetermined reference frequency, and clock signal supply units 41 and 42 switch the clock signals that have different clock frequencies to supply to the DDS 2. When the clock signals are switched to operate the DDS 2, the storage unit 12 stores a combination of a clock frequency f.sub.clk, a reference frequency f.sub.c, and a dividing number N in association with an output frequency f.sub.VCO of the frequency synthesizer 1 such that a spurious frequency does not exist within a predetermined frequency range and a dividing number of a variable frequency divider 302 disposed on a PLL circuit 3 is minimum. Setting units 11 and 24 read setting items stored in the storage unit 12 to set respective units.

A signal generator for producing periodic signals for a measuring apparatus of automation technology. The signals have sequential, discrete signal frequencies, which lie within a predetermined frequency range. A control- and/or computing unit, a clock signal producer are provided, wherein the clock signal producer provides a constant sampling frequency, which is greater than the maximum discrete signal frequency in the predetermined frequency range. A memory unit is provided, in which for each of the discrete signal frequencies the amplitude values of the corresponding periodic signals are stored or storable as a function of the sampling frequency. The control- and/or computing unit reads out the stored or storable amplitude values of the discrete frequencies successively with the sampling frequency of the clock from the memory unit and produces the periodic signals, or forwards for producing. A static filter unit, is also provided with a limit frequency, which lies above the maximum signal frequency and which removes frequency fractions caused by the sampling.