A sine wave generating apparatus comprises: a phase accumulating module, configured to acquire configuration information of a sine wave, and generate address information comprising integer address information and decimal address information; a value searching module, configured to search for first data information and second data information of the sine wave according to the integer address information; an interpolation module, configured to conduct interpolation between the first data information and the second data information, and acquire interpolation original data information of the sine wave according to the decimal address information; a random truncating module, configured to conduct truncation processing on the interpolation original data according to the bit width of the decimal address information and a pseudorandom sequence output value to acquire final interpolation data information of the sine wave; and a sine wave generating module, configured to generate image information of the sine wave according to the final interpolation data information of the sine wave.

Systems and methods are provided for generating a phase compensated numerically controlled signal using a fixed-point algorithm. In one example, a method includes receiving, at a downhole device, parameters including an input frequency and a compensation value. The method further includes converting, based on the parameters, the input frequency to a delta phase value. The method also includes calculating, with the downhole device, an accumulation error for a digital signal. In response to determining that the accumulation error is greater than or equal to the compensation value, the method removes the accumulation error from the digital signal to generate an output signal.

The present invention provides an arbitrary waveform generator based on instruction architecture. To deal with the feature that the instructions and waveform data of the AWG are coupled in the prior art, an instruction set based waveform synthesis controller is employed, and substitutes for the sequence wave generator in the present invention, i.e. an arbitrary waveform generator based on instruction architecture. Thus the time-sharing scheduling in reading the waveform synthesis instruction and the segment waveform data is realized, and the complexity of the hardware is reduced, so that the AWG in present invention can synthesize and generate a complex sequence wave rapidly and efficiently.

Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

A method, device and/or system for generating arbitrary waveforms of a desired shape that can be used for generating a stimulation pulse for medical purposes such as for spinal cord stimulation therapy.

Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

A technique for generating electronic signals includes processing a respective first-level input signal by each of a plurality of first-level channels, including up-sampling the respective first-level input signal and single-sideband (SSB) modulating the up-sampled first-level input signal to produce a respective first-level output signal. The technique further includes processing a respective second-level input signal by each of a plurality of second-level channels, including up-sampling the respective second-level input signal and SSB-modulating the up-sampled second-level input signal to produce a respective second-level output signal. The plurality of second-level channels is arranged in multiple groups assigned to respective first-level channels, and the technique further includes (i) summing together the second-level output signals of the second-level channels in each group, (ii) providing a group sum as the first-level input signal to the first-level channel to which the group is assigned, and summing together the first-level output signals to provide a composite signal.

An apparatus, a signal source, and a method for operating the same are disclosed. The apparatus includes a first signal source, a port, controller, signal synthesizer, and a first timestamp register. The port is adapted to receive a first clock signal that includes a sequence of pulses at a constant clock frequency. The signal synthesizer generates an output signal in response to inputs from the controller, the output signal having a first frequency. The first timestamp register counts pulses from the first clock signal. The controller is adapted to receive a command to change the output signal frequency from the first frequency to a second frequency, the controller causing the signal synthesizer to change the output signal frequency to the second frequency and to generate a frequency change timestamp from the timestamp register indicating a time at which the output signal changed from the first frequency to the second frequency.

Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.